Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: At least one of a system or a method for wirelessly charging a device is provided. A wireless receiver is configured to communicate with a device to be charged to determine a desired charge scenario indicative of power to be supplied to the device. Based upon the desired charge scenario, a resonant frequency of the wireless receiver is set. The resonant frequency, in combination with energy transferred from a wireless transmitter, is configured to induce a current in the wireless receiver. Power is supplied to the device based upon the current induced in the wireless receiver.

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

Abstract: An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.

Abstract: A current balance circuit including a current sensing front end for sensing an output signal from each of a plurality of switching regulators and a current sensor for receiving the sensed output signal and converting the sensed signal into a sensed current signal. The current balance circuit further includes a current averaging circuit for receiving the sensed output signals and determining an average current output for the plurality of switching regulators and a current difference circuit for receiving the average current value and the sensed current signals and determining a current difference for each of the plurality of switching regulators. A calibration circuit is included for receiving the current differences and calculating a calibration value corresponding to each of the plurality of switching regulators which provides an indication of how to adjust a current output of the plurality of switching regulators to balance the current across the plurality of switching regulators.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: A power converter module includes a ground terminal, an input voltage terminal confirmed to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

Abstract: A voltage regulator circuit includes a comparator configured to compare whether an output voltage of the voltage regulator circuit is either equal to or less than a reference voltage; a control unit, coupled to the comparator, and configured to use a duty ratio of the output voltage to an input voltage of the control unit to estimate a time period; a first transistor, coupled to the control unit, and configured to be selectively turned on based on the estimated time period; and an inductor, coupled to the first transistor, configured to conduct an inductor current, wherein when the comparator determines that the output voltage is either equal to or less than the reference voltage, the first transistor is turned on during the estimated time period to allow the inductor current to be increased so as to accordingly increase the output voltage.

Abstract: A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply voltage value and receives a first signal and at least one of the first reference voltage value or the second reference voltage value. The first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value. The second circuit keeps a voltage across two terminals of a first transistor in the second circuit below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.

Abstract: A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.

Abstract: An analog-to-digital converter (“ADC”) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

Abstract: An analog-to-digital converter (“ADC”) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

Abstract: One embodiment of the instant disclosure provides a compact lower power thermal sensor that comprises a combination current generator configured to selectively generate a PTAT and a CTAT current; a convertor configured to generate digital output corresponding to the current mirrored by the current-reuse charge pump; and a current-reuse charge pump coupled between the combination current generator and the convertor, configured to mirror the current generated by the combination current generator and selectively establish a charging/discharging path to/from the convertor. The combination current generator selectively generates the PTAT and the CTAT current in accordance with an output state of the convertor, and the current-reuse charge pump selectively charges and discharges a capacitor of the convertor with the PTAT and the CTAT current in accordance with the output state of the convertor.

Abstract: An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.

Abstract: This application relates to efficient and economical synthetic chemical processes for the preparation of pesticidal thioethers and pesticidal sulfoxides. Further, the present application relates to certain novel compounds necessary for their synthesis. It would be advantageous to produce pesticidal thioethers and pesticidal sulfoxides efficiently and in high yield from commercially available starting materials.

Abstract: A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.