Patents by Inventor Alberto Pagani

Alberto Pagani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for electrical testing of through silicon vias (TSVs)
    Patent number: 9966318
    Abstract: A substrate includes first and second semiconductor layers doped with opposite conductivity type in contact with each other at a PN junction to form a junction diode. At least one through silicon via structure, formed by a conductive region surrounded laterally by an insulating layer, extends completely through the first semiconductor layer and partially through the second semiconductor layer with a back end embedded in, and in physical and electrical contact with, the second semiconductor layer. A first electrical connection is made to the first through silicon via structure and a second electrical connection is made to the first semiconductor layer. A testing current is applied to and sensed at the first and second electrical connections in order to detect a defect in the at least one through silicon via structure.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 8, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • IC with Insulating Trench and Related Methods
    Publication number: 20180122752
    Abstract: A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 3, 2018
    Inventors: Alberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
  • SENSING STRUCTURE OF ALIGNMENT OF A PROBE FOR TESTING INTEGRATED CIRCUITS
    Publication number: 20180113168
    Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.
    Type: Application
    Filed: December 20, 2017
    Publication date: April 26, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVS)
    Publication number: 20180106854
    Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 19, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • ELECTROMAGNETIC SHIELD FOR TESTING INTEGRATED CIRCUITS
    Publication number: 20180100876
    Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.
    Type: Application
    Filed: December 12, 2017
    Publication date: April 12, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS
    Publication number: 20180102353
    Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.
    Type: Application
    Filed: December 12, 2017
    Publication date: April 12, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Pressure sensing device with cavity and related methods
    Patent number: 9939338
    Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alberto Pagani, Federico Giovanni Ziglioli, Bruno Murari
  • Inductive connection structure for use in an integrated circuit
    Patent number: 9929089
    Abstract: An embodiment in a single structure combines a pad comprising a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside the chip itself and at least one inductor that can be used to receive/transmit electromagnetic waves or to supply the chip with power or both. By combining a connection pad and an inductor in a single structure, it is possible to reduce the overall area that otherwise would be occupied exclusively by the inductors, thus reducing the cost and size of integrated circuits that include such a structure.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 27, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Pagani
  • Methods, circuits and systems for a package structure having wireless lateral connections
    Patent number: 9922945
    Abstract: A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 20, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pagani
  • Pressure Sensor with Testing Device and Related Methods
    Publication number: 20180067009
    Abstract: A pressure sensor is for positioning within a structure. The pressure sensor may include a pressure sensor integrated circuit (IC) having a pressure sensor circuit responsive to bending, and a transceiver circuit coupled to the pressure sensor circuit. The pressure sensor may include a support body having a recess therein coupled to the pressure sensor IC so that the pressure sensor IC bends into the recess when the pressure sensor IC is subjected to external pressure.
    Type: Application
    Filed: October 30, 2017
    Publication date: March 8, 2018
    Inventor: Alberto Pagani
  • INTEGRATED ELECTRONIC DEVICE HAVING A TEST ARCHITECTURE, AND TEST METHOD THEREOF
    Publication number: 20180067163
    Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 8, 2018
    Inventor: Alberto Pagani
  • INTEGRATED PRESSURE SENSOR WITH DOUBLE MEASURING SCALE, PRESSURE MEASURING DEVICE INCLUDING THE INTEGRATED PRESSURE SENSOR, BRAKING SYSTEM, AND METHOD OF MEASURING A PRESSURE USING THE INTEGRATED PRESSURE SENSOR
    Publication number: 20180052066
    Abstract: A pressure sensor with double measuring scale includes: a flexible body designed to undergo deflection as a function of a the pressure; piezoresistive transducers for detecting the deflection; a first focusing region designed to concentrate, during a first operating condition, a first value of the pressure in a first portion of the flexible body so as to generate a deflection of the first portion of the flexible body; and a second focusing region designed to concentrate, during a second operating condition, a second value of said pressure in a second portion of the flexible body so as to generate a deflection of the second portion of the flexible body. The piezoresistive transducers correlate the deflection of the first portion of the flexible body to the first pressure value and the deflection of the second portion of the flexible body to the second pressure value.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: Alberto Pagani, Bruno Murari, Marco Ferrera, Domenico Giusti, Daniele Caltabiano
  • CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES
    Publication number: 20180045775
    Abstract: An integrated circuit is fabricated on a semiconductor material die and adapted to be at least partly tested wirelessly. Circuitry for setting a selected radio communication frequency to be used for the wireless test of the integrated circuit is integrated on the semiconductor material die.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 15, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION
    Publication number: 20180040591
    Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 8, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto Pagani, Giovanni Girlando
  • IC with insulating trench and related methods
    Patent number: 9887165
    Abstract: An IC may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The IC may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: February 6, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
  • Electronic system having increased coupling by using horizontal and vertical communication channels
    Patent number: 9881911
    Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 30, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Sensing structure of alignment of a probe for testing integrated circuits
    Patent number: 9880219
    Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 30, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • System and method for electrical testing of through silicon vias (TSVs)
    Patent number: 9874598
    Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 23, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Pagani
  • Electromagnetic shield for testing integrated circuits
    Patent number: 9874586
    Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • SEMICONDUCTOR ELECTRONIC DEVICE WITH IMPROVED TESTING FEATURES AND CORRESPONDING PACKAGING METHOD
    Publication number: 20170373040
    Abstract: An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit and a respective top surface, which extends in a horizontal plane, and are stacked on one another in a vertical direction, transverse to the horizontal plane, and staggered parallel to the same horizontal plane. Provided at a first portion of the top surface is a first plurality of contact pads, and provided at a second portion of the top surface is a second plurality of contact pads. The first portion is covered by a overlying die, and the second portion is exposed and freely accessible. At least some of the contact pads of the first plurality are electrically coupled to internal through silicon vias traversing a substrate of the overlying die to put overlapping dies in electrical contact.
    Type: Application
    Filed: December 2, 2016
    Publication date: December 28, 2017
    Inventor: Alberto Pagani