Abstract: A method includes: receiving, from a vehicle approaching a trust zone, an identifier corresponding to an identity of the vehicle; verifying, by a computing device (e.g., an access server at a gate of the trust zone) and using the identifier, the identity of the vehicle; and comparing the identity of the vehicle with a set of authorized identities stored in a database.

Abstract: Executable code is part of an over-the-air (OTA) update received by, for example, a computing device in a vehicle. In one example, the update is a secure over-the-air (SOTA) update of software that is stored in firmware of a vehicle component (e.g., firmware stored in memory of a storage device or a boot device that are mounted in a vehicle).

Abstract: The present disclosure includes apparatuses, methods, and systems for using memory as a block in a block chain. An embodiment includes a memory, and circuitry configured to generate a block in a block chain for validating data stored in the memory, wherein the block includes a cryptographic hash of a previous block in the block chain and a cryptographic hash of the data stored in the memory, and the block has a digital signature associated therewith that indicates the block is included in the block chain.

Abstract: The present disclosure includes secure device communication. An embodiment includes a processing resource, a memory, and a network management device communication component configured to, send public information to a network attached device communication component, and receive a network attached device public key and an encrypted random string value from the network attached device communication component. The network attached device public key and the random string value are received independent of a type of the network attached device communication component due to the public information. The network management communication component is further configured to decrypt the random string value from the network attached device communication component and send, to the network attached device communication component, a message and a signature to authenticate independent of the type of the network attached device communication component due to the public information.

Abstract: Secure vehicular part communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and a vehicular communication component coupled to the processing resource. The vehicular communication component can be configured to, in response to receiving a part public key and a part signature from a part communication component associated with a vehicular part, verify an identity of the vehicular part based on the part signature. The vehicular communication component can be configured to, in response to verifying the identity, generate a vehicular public key. The vehicular communication component can be configured to encrypt vehicular data using the part public key. The vehicular communication component can be configured to provide the vehicular public key and the vehicular data to the part communication component.

Abstract: Generating, by a computing device, a device secret, the generating comprising: providing, by at least one physical unclonable function (PUF), at least one value; and generating, using a key derivative function (KDF), the device secret, wherein the at least one value provided by the at least one PUF is an input to the KDF; and storing, in memory of the computing device, the generated device secret.

Abstract: The present disclosure relates to an apparatuses and methods for memory management and more particularly to voltage or current detector for a non-volatile memory component that is coupled to a host device or to a System-on-Chip. The memory component includes a memory controller and comprises a voltage or current detector including: a comparator receiving on a voltage input a voltage value Vx; a digital to analog converter coupled to a reference voltage potential and having an output connected to other input of said comparator; a Finite State Machine receiving the output of said comparator and producing digital outputs for the inputs of said memory controller; a current to voltage converter receiving as input a current value Ix to be detected and having an output connected to said Finite State Machine.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: Disclosed are techniques for remotely managing computing devices using blockchain and DICE-RIoT. In one embodiment, a method is disclosed comprising scanning a network to obtain a list of devices on the network; classifying the devices as either controlled or uncontrolled devices; establishing a secure channel with the controlled devices; issuing one or more control commands to the controlled devices over the secure channel, the one or more control commands included within a signed message, the signed message signed using a private key of the sender and verified using a public key of the receiver, the private key and public key generated during the establishing of the secure channel; receiving a response to the control commands; and logging the control commands and the response in a blockchain.

Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: The present disclosure includes apparatuses, methods, and systems for block chain validation of memory commands. An embodiment includes a memory, and circuitry configured to receive a command that is included in a block in a block chain for validating commands to be executed on the memory, wherein the command includes an anti-replay portion that is based on a previous command included in a previous block in the block chain, validate the command using the anti-replay portion of the command, and execute the command on the memory upon validating the command.

Abstract: The present disclosure relates to a system, a method and to a memory device to ensure a secure memory access to a memory device. The memory device is structured and organized with: a first accessible data storage area configured to store data of a host device; a second accessible data storage area configured to store metadata. The second accessible data storage area is organized in groups of sub-fields including at least a first group of flags and at least another field of the same second accessible storage area selectable by the value of one of said flags.

Abstract: System and techniques for a secure wireless lock-actuation exchange are described herein. After receiving a request to actuate a lock from a device, a controller can calculate a challenge counter and then perform verification iterations until an end condition is met—which is a failure of a verification iterations or the number of iterations reaches the challenge count. If the verification iterations reach the challenge count (e.g., there are no failed iterations), then the controller actuates the lock. Each iteration includes an exchange between the device and the controller that the device validates by signing a message with a private key shared by the device and the controller. The exchange also includes a freshness value integrated into the device validation to prevent replay attacks.

Abstract: The present disclosure includes secure device coupling. An embodiment includes a processing resource, memory, and a network management device communication component configured to, identifying a network attached device within a first domain. Generating a domain device secret corresponding to the first domain. Each network attached device within the first domain can share the same domain device secret. Coupling iterations may be performed for each device within the first domain can include: generating a network management device private key and public key. Providing, via short-range communication, the network management device public key and the domain device secret to a network attached device communication component included in each network attached device of the first domain.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication in a traffic control network. An embodiment includes a memory, and circuitry configured to receive a traffic control public key from a traffic control device, wherein the traffic control public key is received in response to providing, to the traffic control device, a request to modify content of the traffic control device, encrypt data corresponding to vehicle information using the traffic control public key, provide, to the traffic control device, the encrypted data to store the data in the traffic control device, and access a network of traffic control devices, including the traffic control device, via the data stored in the traffic control device.

Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.

Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.