Abstract: The present disclosure relates to analyzing a firmware or a finite state machine, decomposing the same into a plurality of routines or states, individuating significative instructions or states, associating each significative instruction or state with a watchpoint, calculating first HASH values of the watchpoints using a HASH function before running the firmware or finite state machine for all allowable paths in the firmware or finite state machine corresponding to a correct working of the same, storing the set of first HASH values as calculated, calculating second HASH values of the watchpoints using a HASH function when running of the firmware or finite state machine, comparing the second HASH value of each watchpoint as calculated with the stored set of first HASH values, and validating the instruction or state of a watchpoint as correct if its second HASH value is comprised in the first HASH values of the allowed paths.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: Secure emergency vehicular communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and an emergency communication component coupled to the processing resource. The emergency communication component can be configured to generate an emergency private key and an emergency public key in response to being within a particular proximity from a vehicular communication component associated with a vehicular entity and in response to receiving a vehicular public key from the vehicular communication component. The emergency communication component can be configured to provide the emergency public key, an emergency signature, and notification data to the vehicular communication component.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.

Abstract: The present disclosure includes apparatuses and methods related to performing a debug operation on an artificial intelligence operation. An example apparatus can include a number of memory arrays and a controller, wherein the controller is configured to perform an artificial intelligence (AI) operation on data stored in the number of memory arrays and perform a debug operation on the AI operation.

Abstract: Disclosed are techniques for remotely controlling autonomous vehicles. In one embodiment, a method is disclosed comprising receiving a message from a first autonomous vehicle, the message including a signed body portion and a triple including components selected from the group consisting of a public identifier of the first autonomous vehicle, a public key of the first autonomous vehicle, and a certificate of the first autonomous vehicle; authenticating the message by verifying the certificate of the first autonomous vehicle; logging the message into a blockchain storage structure, the blockchain storage structure storing a plurality of blocks, each blocking including the signed body portion; and executing one or more orders included within the signed body portion.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: Disclosed are techniques for providing driver assistance to a non-autonomous vehicle while operating in an autonomous vehicle environment. In one embodiment, a method is disclosed comprising establishing a secure connection with an object selected from a group consisting of a road and lane of a road; receiving, from the object, a packet, the packet describing a condition of the object; validating the packet; generating an augmented display using data within the packet; and displaying the augmented display in a vehicle.

Abstract: A parking system having parking lots and server computers configured to control access to the parking lots. The server computers are connected via a communications network to form a peer to peer network of computing nodes. The peer to peer network of computing nodes hosts a decentralized, distributed database that stores activity records of parking spaces in the parking lots. The peer to peer network can include vehicles planning to use parking services of the parking lots and/or mobile devices connected to infotainment systems of the vehicles. Alternatively, the peer to peer network is formed by parking applications running in the vehicles and/or the mobile devices. The records in the decentralized, distributed database provide parking space availability information and/or can be used to regulate and/or plan parking reservation, usage, and navigational guidance to reach available parking spaces.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

Abstract: A method includes: receiving, by a computing device of a first vehicle, a command from a host device; in response to receiving the command, storing a new device secret in memory; generating, by the computing device using the new device secret, a triple comprising an identifier, a certificate, and a public key; and sending, by the computing device, the triple to a second vehicle, where the second vehicle is configured to verify an identity of the first vehicle using the triple.

Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: The present disclosure includes apparatuses, methods, and systems for securing sensor communication. An embodiment includes a memory having instructions executable by the processing resource, and a sensor coupled to the processing resource and the memory. Wherein, the sensor is configured to collect sensor data and generate and provide a sensor public key, a sensor public identification, and a sensor identification certificate to a sensor fusion unit.