Abstract: The present disclosure includes apparatuses, methods, and systems for validating an electronic control unit of a vehicle. An embodiment includes a memory, and circuitry configured to generate a run-time cryptographic hash based on an identification (ID) number of an electronic control unit of a vehicle and compare the run-time cryptographic hash with a cryptographic hash stored in a portion of the memory.

Abstract: An example memory device includes an array of memory cells, a plurality of boundary cells, mixed pads connected to the memory cells, high speed pads connected to the boundary cells, a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive at least first and second input signals, and the three state multiplexer block is connected to the mixed pads. The example memory device further includes an enabling circuit connected to a mixed pad and configured to receive an external enabling signal and provide the three state MUX with an internal enabling signal, and comprising: a tester presence detector circuit connected to the mixed pad and configured to provide a presence signal to a logical gate, the logical gate having input terminals connected to the tester presence detector circuit and configured to provide the internal enabling signal.

Abstract: The present disclosure includes apparatuses, methods, and systems for error identification on executed code. An embodiment includes memory and circuitry configured to read data stored in a secure array of the memory, identify a different memory having an error correcting code (ECC) corresponding to the read data of the memory, execute an integrity check to compare the ECC to the read data of the memory; and take an action in response to the comparison of the read data of the memory and the ECC, wherein the comparison indicates that the ECC identified an error in the read data of the memory.

Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.

Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.

Abstract: The present disclosure relates to an apparatus comprising: a host device or a System-on-Chip: a memory component having an independent structure and including at least an array of memory cells organized in sub-arrays with associated decoding and sensing circuitry; a JTAG interface in said at least an array of memory cells including a boundary-scan architecture; an instruction register in said boundary-scan architecture of the JTAG interface including at least a couple of Bits indicative of the presence of a Test Data Input (TDI) signal. The apparatus has an extended TDI functionality using the data IO to improve the overall performances. A method for improving the communication between a Host or SoC device and an associated independent memory component is also disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication between an intermediary device and a network. An example apparatus includes a memory, and circuitry. The circuitry is configured to determine, in response to receipt of a request for information corresponding to a particular category, an identifier associated with the particular category. The circuitry is further configured to provide, along with a signature, the determined identifier to a network device, wherein the requested information are received in response to the signature being verified by network device.

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Abstract: A vehicle having the first ANN model initially installed therein to generate outputs from inputs generated by one or more sensors of the vehicle. The vehicle selects an input based on an output generated from the input using the first ANN model. The vehicle has a module to incrementally train the first ANN model through unsupervised machine learning from sensor data that includes the input selected by the vehicle. Optionally, the sensor data used for the unsupervised learning may further include inputs selected by other vehicles in a population. Sensor inputs selected by vehicles are transmitted to a centralized computer server, which trains the first ANN model through supervised machine learning from sensor received inputs from the vehicles in the population and generates a second ANN model as replacement of the first ANN model previously incrementally improved via unsupervised machine learning in the population.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure electronic control unit updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an electronic control unit update for electronic control unit data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the electronic control unit data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

Abstract: An example apparatus comprises a memory resource configured to store a private key associated with a vehicle and store a data matrix comprising data corresponding to operation of the vehicle. The apparatus may further include a processing resource configured to generate a first secure message comprising data corresponding to the vehicle, transmit the first secure message, receive a second secure message comprising an updated data matrix, and update the data matrix based, at least in part, on the updated data matrix.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

Abstract: The present disclosure includes apparatuses, methods, and systems for verifying a vehicular identity. An embodiment includes a processing resource, memory, and a vehicular communication component configured to verify an identity of the particular vehicle using a public key, wherein the public key is received in response to a departure of the particular vehicle, and request, in response to verifying the identity of the particular vehicle, data corresponding to information associated with the departure of the particular vehicle.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication for a key replacement. An embodiment includes a processing resource, memory having a first operator's key, and a vehicular communication component. The vehicular communication component can be configured to provide, to a server, a public key generated along with a private key and decrypt, in response to receipt of a second operator's key (e.g., received in response to providing the public key to the server) encrypted using the public key, the second operator's key using the private key. The vehicular communication component can be configured to replace, in response to decrypting the encrypted second operator's key, the first operator's key with the second operator's key.

Abstract: A method includes receiving, by a computing device, a message from a host device. In response to receiving the message, the computing device generates an identifier, a certificate, and a key. The identifier is associated with an identity of the computing device, and the certificate is generated using the message. The computing device sends the identifier, the certificate, and the key to the host device. The host device verifies the identity of the computing device using the identifier, the certificate, and the key.

Abstract: Secure medical apparatus communication is described herein. An example apparatus can include a processor and an apparatus communication component. The apparatus communication component can be coupled to the processor and can be configured to, in response to receiving data from an external communication component, generate an apparatus private key and an apparatus public key, provide the apparatus public key and data to the external communication component, receive data from the external communication component in response to providing the apparatus public key and data to the external communication component, decrypt the received data using the apparatus private key, verify an identity of the external communication component, and in response to verifying the identity of the external communication component, perform an operation on the medical apparatus using the received data.

Abstract: The present disclosure relates to a detector comprising a comparator receiving on a voltage input a voltage value to be detected; a digital to analog converter coupled to a reference voltage potential having an output connected to another input of the comparator; and a Finite State Machine receiving an output of the comparator and producing digital outputs for inputs of a memory controller.

Abstract: Disclosed are techniques for providing driver assistance to a non-autonomous vehicle while operating in an autonomous vehicle environment. In one embodiment, a method is disclosed comprising establishing a secure connection with an object selected from a group consisting of a road and lane of a road; receiving, from the object, a packet, the packet describing a condition of the object; validating the packet; generating an augmented display using data within the packet; and displaying the augmented display in a vehicle.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).