Abstract: An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

Abstract: Techniques for calculating a hash value of a single secure array of memory blocks in a sequential set of dice. The array can be defined by a set of address-size pairs. Each pair provides a pointer by including an address of a memory block and a size of the block. The hash value can be calculated by: for each die that is not the last die, partially applying a hash function, without final padding, to the memory blocks of the secure array in the die to generate a partial digest. And, for the last die, fully applying the hash function, with the final padding, to the memory blocks of the secure array in the last die to generate the hash value of the secure array, which can include adding an accumulation of partial digests to data from the last die as a basis for the generation of the hash value.

Abstract: A method includes: receiving, by a computing device of a first vehicle, a command from a host device; in response to receiving the command, storing a new device secret in memory; generating, by the computing device using the new device secret, a triple comprising an identifier, a certificate, and a public key; and sending, by the computing device, the triple to a second vehicle, where the second vehicle is configured to verify an identity of the first vehicle using the triple.

Abstract: The present disclosure includes apparatuses, methods, and systems for run-time code execution validation. An embodiment includes a memory, and circuitry configured to monitor run-time executable code stored in a secure array of the memory device and receive an indication that a portion of the run-time executable code executed, wherein the indication includes a received Message Authentication Code (MAC) and take an action in response to the indication that the portion of the run-time executable code failed to execute.

Abstract: Secure vehicular part communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and a vehicular communication component coupled to the processing resource. The vehicular communication component can be configured to, in response to receiving a part public key and a part signature from a part communication component associated with a vehicular part, verify an identity of the vehicular part based on the part signature. The vehicular communication component can be configured to, in response to verifying the identity, generate a vehicular public key. The vehicular communication component can be configured to encrypt vehicular data using the part public key. The vehicular communication component can be configured to provide the vehicular public key and the vehicular data to the part communication component.

Abstract: The present disclosure includes secure communication between a vehicle and a remote device. An embodiment includes a processing resource, memory, and a vehicular communication component configured to, in response to receiving a request from a remote communication component to switch a state of a lock, calculate a challenge count for the request, generate a vehicular private key and a vehicular public key, perform a number of verification iterations, each respective verification iteration including providing the public key to the remote communication component, receiving, from the remote communication component, code for switching the lock state, verifying the remote communication component's identity, and incrementing a counter in response to verifying the remote communication component's identity, and decrypt the code using the private key and switch the lock state in response to the counter being incremented to a value equal to or greater than the challenge count.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: A method and apparatus according to the invention can include energizing a wireless communication device coupled to a processor of a vehicular entity thus establishing a secure channel or communication area around the vehicular entity; exchanging information and data with other vehicular entities entering the established channel or communication area; regulating some vehicle parameters of said vehicular entity for driving the departure and/or travelling of the vehicular entity according to the received information and data.

Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating data stored in memory using cryptographic hashes. An embodiment includes a memory, and circuitry configured to divide the memory into a plurality of segments, wherein each respective segment is associated with a different cryptographic hash, validate, during a powering of the memory, data stored in each respective one of a first number of the plurality of segments using the cryptographic hash associated with that respective segment, and validate, after the powering of the memory, data stored in a second number of the plurality of segments, data stored in each respective one of a second number of the plurality of segments using the cryptographic hash associated with that respective segment.

Abstract: An apparatus can have a processor configured to determine a length of time that a vehicle is in a region and to determine whether the vehicle needs to be configured for the region based on the determined length of time.

Abstract: The present disclosure includes apparatuses, methods, and systems for securing sensor communication. An embodiment includes a memory having instructions executable by the processing resource, and a sensor coupled to the processing resource and the memory. Wherein, the sensor is configured to collect sensor data and generate and provide a sensor public key, a sensor public identification, and a sensor identification certificate to a sensor fusion unit.

Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

Abstract: A vehicle having the first ANN model initially installed therein to generate outputs from inputs generated by one or more sensors of the vehicle. The vehicle selects an input based on an output generated from the input using the first ANN model. The vehicle has a module to incrementally train the first ANN model through unsupervised machine learning from sensor data that includes the input selected by the vehicle. Optionally, the sensor data used for the unsupervised learning may further include inputs selected by other vehicles in a population. Sensor inputs selected by vehicles are transmitted to a centralized computer server, which trains the first ANN model through supervised machine learning from sensor received inputs from the vehicles in the population and generates a second ANN model as replacement of the first ANN model previously incrementally improved via unsupervised machine learning in the population.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating an electronic control unit of a vehicle. An embodiment includes a memory, and circuitry configured to generate a run-time cryptographic hash based on an identification (ID) number of an electronic control unit of a vehicle and compare the run-time cryptographic hash with a cryptographic hash stored in a portion of the memory.

Abstract: The present disclosure includes apparatuses, methods, and systems for using memory as a block in a block chain. An embodiment includes a memory, and circuitry configured to generate a block in a block chain for validating data stored in the memory, wherein the block includes a cryptographic hash of a previous block in the block chain and a cryptographic hash of the data stored in the memory, and the block has a digital signature associated therewith that indicates the block is included in the block chain.

Abstract: Secure communication in accessing a network is described herein. An example apparatus can include a memory and a processor coupled to the memory. The processor can be configured to receive an identity public key from the identity device. The identity public key can be received in response to providing, to the identity device, a request to modify content of the identity device. The processor can be further configured to encrypt data corresponding to subscriber information using the identity public key, provide (to the identity device) the encrypted data to store the subscriber information in the identity device, and access a network operated by a network operator via the data stored in the identity device.

Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.