Abstract: A method and apparatus to recognize transported passengers and goods are disclosed herein. One example includes an apparatus comprising a processor unit on a vehicular entity, a communication component coupled to the processor unit, and a memory portion associated to the processor unit and structured to store information and data received through the communication component about at least one of passengers, luggage and/or goods on the vehicular entity, with the communication component being activated by a presence of the at least one of the passengers, luggage and/or goods on the vehicular entity.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating an electronic control unit of a vehicle. An embodiment includes a memory, and circuitry configured to generate a run-time cryptographic hash based on an identification (ID) number of an electronic control unit of a vehicle and compare the run-time cryptographic hash with a cryptographic hash stored in a portion of the memory.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: Secure emergency vehicular communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and an emergency communication component coupled to the processing resource. The emergency communication component can be configured to generate an emergency private key and an emergency public key in response to being within a particular proximity from a vehicular communication component associated with a vehicular entity and in response to receiving a vehicular public key from the vehicular communication component. The emergency communication component can be configured to provide the emergency public key, an emergency signature, and notification data to the vehicular communication component.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: An example apparatus can include a processor and an external communication component. The external communication component can be coupled to the processor and can be configured to, in response to determining a vehicular entity is within a particular proximity to the external communication component, generate an external private key and an external public key. The external communication component can further provide the external public key and data to a vehicular communication component associated with the vehicular entity. The external communication component can further receive data from the vehicular communication component in response to providing the external public key and data to the vehicular communication component. The external communication component can further decrypt the received data using the external private key, and provide a service to the vehicular entity based on the decrypted received data.

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Abstract: An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.

Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.

Abstract: The present disclosure includes apparatuses, methods, and systems for run-time code execution validation. An embodiment includes a memory, and circuitry configured to monitor run-time executable code stored in a secure array of the memory device and receive an indication that a portion of the run-time executable code executed, wherein the indication includes a received Message Authentication Code (MAC) and take an action in response to the indication that the portion of the run-time executable code failed to execute.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: User data stored in memory of a shared vehicle is managed in a secure manner. In some embodiments, user data stored in the vehicle is deleted in response to receiving a communication that initiates closing of usage of the vehicle (e.g., from a client device of a user that is operating the vehicle). A new user of a vehicle is prevented from being able to read or use private data of a prior user. In some embodiments, when authorizing usage of a vehicle by a new user, the vehicle is caused to delete the prior user data. After the prior user data has been deleted, a notification is received from the vehicle confirming that the vehicle has deleted the prior user data.

Abstract: The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: The present disclosure includes apparatuses, methods, and systems for error identification on executed code. An embodiment includes memory and circuitry configured to read data stored in a secure array of the memory, identify a different memory having an error correcting code (ECC) corresponding to the read data of the memory, execute an integrity check to compare the ECC to the read data of the memory; and take an action in response to the comparison of the read data of the memory and the ECC, wherein the comparison indicates that the ECC identified an error in the read data of the memory.

Abstract: An example apparatus comprises a memory resource configured to store a private key associated with a vehicle and store a data matrix comprising data corresponding to operation of the vehicle. The apparatus may further include a processing resource configured to generate a first secure message comprising data corresponding to the vehicle, transmit the first secure message, receive a second secure message comprising an updated data matrix, and update the data matrix based, at least in part, on the updated data matrix.

Abstract: A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.