Abstract: A method for updating a sensor system, the method including: performing at an update server side the steps of: retrieving a pre-shared sensor key associated with the sensor system, calculating a server signature based on update data and the retrieved sensor key, and transmitting the update data and the calculated server signature to the sensor system; and performing at the sensor system the steps of: receiving the update data and the calculated server signature, retrieving the pre-shared sensor key stored in a register, calculating a sensor system signature based on the update data and the pre-shared sensor key, comparing the sensor system signature with the server signature and processing the update data if the sensor system signature and the server signature are identical.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: A method and apparatus according to the invention can include energizing a wireless communication device coupled to a processor of a vehicular entity thus establishing a secure channel or communication area around the vehicular entity; exchanging information and data with other vehicular entities entering the established channel or communication area; regulating some vehicle parameters of said vehicular entity for driving the departure and/or travelling of the vehicular entity according to the received information and data.

Abstract: Various examples are directed to systems and methods for managing a memory system. The memory system may generate a first encrypted physical address using a first clear physical address. The memory system may generate a first encrypted logical-to-physical (L2P) pointer indicating the first logical address and a first encrypted physical address. The memory system may send the first encrypted L2P pointer to a host device for storage at a host memory.

Abstract: The present disclosure includes apparatuses and methods related to an artificial intelligence accelerator in memory. An example apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating data stored in memory using cryptographic hashes. An embodiment includes a memory, and circuitry configured to divide the memory into a plurality of segments, wherein each respective segment is associated with a different cryptographic hash, validate, during a powering of the memory, data stored in each respective one of a first number of the plurality of segments using the cryptographic hash associated with that respective segment, and validate, after the powering of the memory, data stored in a second number of the plurality of segments, data stored in each respective one of a second number of the plurality of segments using the cryptographic hash associated with that respective segment.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: The present disclosure includes apparatuses and methods related to memory with an artificial intelligence (AI) accelerator. An example apparatus can include receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode and perform AI operations using an AI accelerator based on a status of a number of register on the controller. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations (e.g., logic operations, among other operations) associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: Disclosed are techniques for improving an advanced driver-assistance system (ADAS) using a secure channel area. In one embodiment, a method is disclosed comprising establishing a secure channel area extending from at least one side of a first vehicle; detecting a presence of a second vehicle in the secure channel area; establishing a secure connection with the second vehicle upon detecting the presence; exchanging messages between the first vehicle and the second vehicle, the messages including a position and speed of a sending vehicle; taking control of a position and speed of the first vehicle based on the contents of the messages; and releasing control of the position and speed of the first vehicle upon detecting that the secure connection was released.

Abstract: The present disclosure includes apparatuses, methods, and systems for block chain validation of memory commands. An embodiment includes a memory, and circuitry configured to receive a command that is included in a block in a block chain for validating commands to be executed on the memory, wherein the command includes an anti-replay portion that is based on a previous command included in a previous block in the block chain, validate the command using the anti-replay portion of the command, and execute the command on the memory upon validating the command.

Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication in a traffic control network. An embodiment includes a memory, and circuitry configured to receive a traffic control public key from a traffic control device, wherein the traffic control public key is received in response to providing, to the traffic control device, a request to modify content of the traffic control device, encrypt data corresponding to vehicle information using the traffic control public key, provide, to the traffic control device, the encrypted data to store the data in the traffic control device, and access a network of traffic control devices, including the traffic control device, via the data stored in the traffic control device.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication for a key replacement. An embodiment includes a processing resource, memory having a first operator's key, and a vehicular communication component. The vehicular communication component can be configured to provide, to a server, a public key generated along with a private key and decrypt, in response to receipt of a second operator's key (e.g., received in response to providing the public key to the server) encrypted using the public key, the second operator's key using the private key. The vehicular communication component can be configured to replace, in response to decrypting the encrypted second operator's key, the first operator's key with the second operator's key.

Abstract: Computing nodes in a peer-to-peer network that can receive data about an accident in response to a vehicle having an accident. A computing device in the peer-to-peer network can generate a record of the data and store, in persistent storage, a copy of the record. The computing device can also transmit the record, via peer-to-peer connections, to other computing nodes in the network. The nodes in the network, when receiving the record, can each store a copy of the record and broadcast the record to one or more additional computing nodes in the network to cause the one or more additional computing nodes to store one or more additional copies of the record. Also, in response to an inquiry about the accident, the node can provide the record. And the node can participate in a determination of a network consensus in the network about validity of the record.

Abstract: The present disclosure includes apparatuses and methods related to defining activation functions for artificial intelligence (AI) operations. An example apparatus can include a number of memory arrays and a controller, wherein the controller includes a number of activations function registers, wherein the number of activation function registers define activation functions for artificial intelligence (AI) operations performed by the apparatus.

Abstract: A method and a system may include a light detection and ranging (LiDAR) system having one or more redundant channels, as well as software executed by a microcontroller, or controller, to use the redundant channels in response to and instead of detected, failed channels. For example, inputs to a failed channel from photodiodes may be replaced from the failed channel to a redundant channel. The substitution of the redundant channel for the failed channel may occur seamlessly, allowing for uninterrupted operation of the LiDAR system.

Abstract: An example apparatus comprises a processing resource coupled to a memory resource. The processing resource may be configured to execute instructions stored on the memory resource to generate a first secure key including a private key stored by a vehicle, generate a first secure message including the first secure key, transmit the first secure message over a vehicle bus to a vehicle part associated with the vehicle, and receive, from the vehicle part, a second secure message including at least one of a vehicle identification number (VIN) and a configuration parameter corresponding to the vehicle part in response to a determination that the first secure key matches a secure key corresponding to the vehicle part.

Abstract: An example apparatus comprises a memory resource configured to store data and transmit data. The apparatus may further include a safety controller coupled to the memory resource configured to receive the data from the memory resource, receive latched data from an application controller, and determine whether to allow an output of commands from the application controller in response to a comparison of the data from the memory resource and the latched data from the application controller.

Abstract: An apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.