Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells able to manage serial and parallel data; mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine; high speed pads connected to the boundary cells through high speed paths; a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads; ESD networks connected to the mixed pads; an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal; wherein the enabling circuit comprises: a tester presence detector circuit connected to the mixed pad; and a logical gate having respective input terminals connected to t

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Abstract: The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

Abstract: Secure vehicular part communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and a vehicular communication component coupled to the processing resource. The vehicular communication component can be configured to, in response to receiving a part public key and a part signature from a part communication component associated with a vehicular part, verify an identity of the vehicular part based on the part signature. The vehicular communication component can be configured to, in response to verifying the identity, generate a vehicular public key. The vehicular communication component can be configured to encrypt vehicular data using the part public key. The vehicular communication component can be configured to provide the vehicular public key and the vehicular data to the part communication component.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: The present disclosure includes apparatuses and methods related to defining activation functions for artificial intelligence (AI) operations. An example apparatus can include a number of memory arrays and a controller, wherein the controller includes a number of activations function registers, wherein the number of activation function registers define activation functions for artificial intelligence (AI) operations performed by the apparatus.

Abstract: System and techniques for a secure wireless lock-actuation exchange are described herein. After receiving a request to actuate a lock from a device, a controller can calculate a challenge counter and then perform verification iterations until an end condition is met—which is a failure of a verification iterations or the number of iterations reaches the challenge count. If the verification iterations reach the challenge count (e.g., there are no failed iterations), then the controller actuates the lock. Each iteration includes an exchange between the device and the controller that the device validates by signing a message with a private key shared by the device and the controller. The exchange also includes a freshness value integrated into the device validation to prevent replay attacks.

Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: The present disclosure includes methods and apparatuses comprising a processor and an external communication component coupled to the processor. The external communication component, in response to determining that an approaching entity is within a particular proximity of the external communication component, is configured to generate an external private key and an external public key, provide the external public key to a communication component of the approaching entity, receive data from the communication component of the approaching entity in response to providing the external public key to the communication component of the approaching entity, decrypt the received data using the external private key, and provide authorization to the approaching entity to transit through a limited access gate based on the decrypted received data.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: A method for updating a sensor system, the method including: performing at an update server side the steps of: retrieving a pre-shared sensor key associated with the sensor system, calculating a server signature based on update data and the retrieved sensor key, and transmitting the update data and the calculated server signature to the sensor system; and performing at the sensor system the steps of: receiving the update data and the calculated server signature, retrieving the pre-shared sensor key stored in a register, calculating a sensor system signature based on the update data and the pre-shared sensor key, comparing the sensor system signature with the server signature and processing the update data if the sensor system signature and the server signature are identical.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: A method and apparatus according to the invention can include energizing a wireless communication device coupled to a processor of a vehicular entity thus establishing a secure channel or communication area around the vehicular entity; exchanging information and data with other vehicular entities entering the established channel or communication area; regulating some vehicle parameters of said vehicular entity for driving the departure and/or travelling of the vehicular entity according to the received information and data.

Abstract: Various examples are directed to systems and methods for managing a memory system. The memory system may generate a first encrypted physical address using a first clear physical address. The memory system may generate a first encrypted logical-to-physical (L2P) pointer indicating the first logical address and a first encrypted physical address. The memory system may send the first encrypted L2P pointer to a host device for storage at a host memory.

Abstract: The present disclosure includes apparatuses and methods related to an artificial intelligence accelerator in memory. An example apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating data stored in memory using cryptographic hashes. An embodiment includes a memory, and circuitry configured to divide the memory into a plurality of segments, wherein each respective segment is associated with a different cryptographic hash, validate, during a powering of the memory, data stored in each respective one of a first number of the plurality of segments using the cryptographic hash associated with that respective segment, and validate, after the powering of the memory, data stored in a second number of the plurality of segments, data stored in each respective one of a second number of the plurality of segments using the cryptographic hash associated with that respective segment.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: Disclosed are techniques for improving an advanced driver-assistance system (ADAS) using a secure channel area. In one embodiment, a method is disclosed comprising establishing a secure channel area extending from at least one side of a first vehicle; detecting a presence of a second vehicle in the secure channel area; establishing a secure connection with the second vehicle upon detecting the presence; exchanging messages between the first vehicle and the second vehicle, the messages including a position and speed of a sending vehicle; taking control of a position and speed of the first vehicle based on the contents of the messages; and releasing control of the position and speed of the first vehicle upon detecting that the secure connection was released.

Abstract: The present disclosure includes apparatuses and methods related to memory with an artificial intelligence (AI) accelerator. An example apparatus can include receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode and perform AI operations using an AI accelerator based on a status of a number of register on the controller. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations (e.g., logic operations, among other operations) associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: The present disclosure includes apparatuses, methods, and systems for block chain validation of memory commands. An embodiment includes a memory, and circuitry configured to receive a command that is included in a block in a block chain for validating commands to be executed on the memory, wherein the command includes an anti-replay portion that is based on a previous command included in a previous block in the block chain, validate the command using the anti-replay portion of the command, and execute the command on the memory upon validating the command.