Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: A plurality of dice having at least a first die and a second die. The first die can generate a measure of the first die using a cryptographic algorithm, a public key and a private key, and a digital signature according to the measure and the private key. The digital signature can include a digest encrypted by the private key. The digest can include the measure. The first die can communicate the measure, the digital signature, and the public key to the second die. The second die can store a validation code representative of a measure of the first die and validate the digital signature using the public key as well validate the measure by comparing the measure to the validation code.

Abstract: A data transmitter is disclosed. The data transmitter includes a digest generator configured in response to receiving a set of data from a data source to generate a digest from the set of data using a cryptographic primitive. The data transmitter further includes a packet generator configured to generate a series of one or more packets carrying the set of data for transmission, wherein each packet in the series includes a header, the set of data, a footer and the digest.

Abstract: Systems and methods for monitoring and analyzing vehicle data within a vehicle and providing analytical processing data to prospective users of vehicles are disclosed. In one embodiment, a method is disclosed comprising monitoring a communications bus installed within a vehicle, the communications bus transmitting data recorded by one or more sensors installed within the vehicle; detecting a message broadcast on the communications bus; extracting an event from the message, the extraction based on a pre-defined list of event types; storing the event in a secure storage device installed within the vehicle; determining that a transfer condition has occurred; and transferring the event data to a remote server in response to determining that the transfer condition has occurred.

Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: A method and apparatus according to the invention can include energizing a wireless communication device coupled to a processor of a vehicular entity thus establishing a secure channel or communication area around the vehicular entity; exchanging information and data with other vehicular entities entering the established channel or communication area; regulating some vehicle parameters of said vehicular entity for driving the departure and/or travelling of the vehicular entity according to the received information and data.

Abstract: The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.

Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: A method and apparatus to recognize transported passengers and goods are disclosed herein. One example includes an apparatus comprising a processor unit on a vehicular entity, a communication component coupled to the processor unit, and a memory portion associated to the processor unit and structured to store information and data received through the communication component about at least one of passengers, luggage and/or goods on the vehicular entity, with the communication component being activated by a presence of the at least one of the passengers, luggage and/or goods on the vehicular entity.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating an electronic control unit of a vehicle. An embodiment includes a memory, and circuitry configured to generate a run-time cryptographic hash based on an identification (ID) number of an electronic control unit of a vehicle and compare the run-time cryptographic hash with a cryptographic hash stored in a portion of the memory.

Abstract: An example apparatus can include a processor and an external communication component. The external communication component can be coupled to the processor and can be configured to, in response to determining a vehicular entity is within a particular proximity to the external communication component, generate an external private key and an external public key. The external communication component can further provide the external public key and data to a vehicular communication component associated with the vehicular entity. The external communication component can further receive data from the vehicular communication component in response to providing the external public key and data to the vehicular communication component. The external communication component can further decrypt the received data using the external private key, and provide a service to the vehicular entity based on the decrypted received data.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an update for data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: Secure emergency vehicular communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and an emergency communication component coupled to the processing resource. The emergency communication component can be configured to generate an emergency private key and an emergency public key in response to being within a particular proximity from a vehicular communication component associated with a vehicular entity and in response to receiving a vehicular public key from the vehicular communication component. The emergency communication component can be configured to provide the emergency public key, an emergency signature, and notification data to the vehicular communication component.

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Abstract: An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.