Patents by Inventor Aleksandar Aleksov

Aleksandar Aleksov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210358855
    Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Applicant: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Henning Braunisch, Brandon Rawlings, Johanna Swan, Shawna Liff
  • Publication number: 20210358872
    Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Aleksandar ALEKSOV, Telesphor KAMGAING
  • Publication number: 20210343673
    Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.
    Type: Application
    Filed: July 2, 2021
    Publication date: November 4, 2021
    Inventors: Changhua LIU, Xiaoying GUO, Aleksandar ALEKSOV, Steve S. CHO, Leonel ARANA, Robert MAY, Gang DUAN
  • Publication number: 20210343635
    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Johanna Swan, Henning Braunisch, Aleksandar Aleksov, Shawna Liff, Brandon Rawlings, Veronica Strong
  • Patent number: 11158917
    Abstract: Embodiments may relate to an assembly that includes a first package substrate with a first electromagnetic cavity. The assembly may further include a second package substrate with a second electromagnetic cavity that is adjacent to the first electromagnetic cavity. The first and second electromagnetic cavities may form a millimeter wave (mmWave) resonant cavity of a mmWave filter. Other embodiments may be described or claimed.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Feras Eid, Johanna M. Swan
  • Patent number: 11147197
    Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
  • Publication number: 20210305668
    Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Brandon C. MARIN, Jeremy D. ECTON, Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Yonggang LI, Dilan SENEVIRATNE
  • Patent number: 11133263
    Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Henning Braunisch, Brandon Rawlings, Johanna Swan, Shawna Liff
  • Publication number: 20210296175
    Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Patent number: 11107781
    Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Kristof Kuwawi Darmawikarta, Robert Alan May, Aleksandar Aleksov, Telesphor Kamgaing
  • Publication number: 20210265732
    Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventors: Feras EID, Sasha N. OSTER, Telesphor KAMGAING, Georgios C. DOGIAMIS, Aleksandar ALEKSOV
  • Publication number: 20210265288
    Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 26, 2021
    Applicant: INTEL CORPORATION
    Inventors: GEORGIOS DOGIAMIS, SASHA OSTER, JOHANNA SWAN, SHAWNA LIFF, ADEL ELSHERBINI, TELESPHOR KAMGAING, ALEKSANDAR ALEKSOV
  • Patent number: 11101205
    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Johanna Swan, Henning Braunisch, Aleksandar Aleksov, Shawna Liff, Brandon Rawlings, Veronica Strong
  • Patent number: 11095012
    Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • Patent number: 11088103
    Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Changhua Liu, Xiaoying Guo, Aleksandar Aleksov, Steve S. Cho, Leonel Arana, Robert May, Gang Duan
  • Patent number: 11081768
    Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Jeremy D. Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Yonggang Li, Dilan Seneviratne
  • Publication number: 20210233856
    Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 11062947
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Publication number: 20210202403
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20210202404
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan