Abstract: The anti-windup circuit generally has a voltage clamping device in series with a current limiting device operatively connectable to the output current path of a feedback compensator; the feedback compensator being part of a switch-mode power supply (SMPS) having an input voltage source and a load and generating constrained control values required to generate control on-off actions for tight power regulation. The inclusion of the disclosed anti-windup circuit in an SMPS may lead to hardware based overvoltage protection, reduced overall size and faster response to load changes.

Abstract: A quasi-resonant auto-tuning controller includes a zero-voltage crossing detection circuit and a valley tuning finite-state machine having a look-up table. The zero-voltage crossing detection circuit receives a reference voltage and receives an auxiliary signal from an auxiliary winding. The zero-voltage crossing detection circuit produces a comparison signal having pulses when the auxiliary signal is less than the reference voltage. The valley tuning finite-state machine produces a divided pulse width based on the comparison signal, stores the divided pulse width of each pulse in the look-up table, determines, from the comparison signal, that the auxiliary signal is less than the reference voltage, waits a time period corresponding to the divided pulse width stored in the look-up table if the auxiliary signal is less than the reference voltage, and produces a valley point signal after waiting the time period.

Abstract: A single-mode quasi constant frequency controller apparatus for controlling output voltage deviation during one or more load transients, the controller apparatus comprising: a converter receiving one or more operational control parameters; a load tracking modulator configured to receive sensory inputs representative of a capacitor current polarity, and to control one or more power transistors of the converter such that an inductor current matches a load current cycle and reconstructs a desired inductor current ripple by splitting both an on-time for inductor charging and an off-time for inductor discharging into a current correction phase (CCP) and a ripple reconstruction phase (RRP), the load tracking modulator communicating the one or more operational control parameters for controlling the one or more power transistors.

Abstract: A power converter controller includes an analog to digital converter (ADC) to generate a digital representation of a feedback signal of a power converter, the feedback signal being received from a compensator of the power converter and being based on an output voltage of the power converter. A nonlinear gain block of the power converter controller receives the digital representation of the feedback signal and generates a transformed digital representation of the feedback signal using a nonlinear function. A switch control block of the power converter controller controls an on-time of a primary-side switch of the power converter based on the transformed digital representation of the feedback signal.

Abstract: A method involves determining that a power converter is in a no-load or ultra-light load mode of operation. In response to determining that the power converter is in a no-load or ultra-light load mode of operation, a voltage amplitude of a feedback signal of the power converter is allowed to rise towards a voltage amplitude that is greater than or equal to a first threshold voltage level. Upon determining that the voltage amplitude of the feedback signal is greater than or equal to the first threshold voltage level, a first sequence of enabling pulses are issued to a primary side switch of the power converter to reduce a voltage amplitude of the feedback signal. Upon determining that the voltage amplitude of the feedback signal is greater than or equal to a second threshold voltage level, a normal mode of operation of the power converter is entered.

Abstract: A method involves controlling, for a duration of a first modulation period, a first average off-time of a main switch of a power converter such that the first average off-time of the main switch corresponds to a first intermediate valley number of multiple intermediate valley numbers, an average of the intermediate valley numbers corresponding to a target number of valleys of a resonant waveform at a drain node of the main switch. A second intermediate valley number of the intermediate valley numbers is selected upon expiration of the first modulation period. A difference of the second intermediate valley number and the first intermediate valley number is equal to a fractional valley number offset. A second average off-time of the main switch is controlled for a duration of a second modulation period such that the second average off-time of the main switch corresponds to the second intermediate valley number.

Abstract: A power converter controller includes an analog to digital converter (ADC) to generate a digital representation of a feedback signal of a power converter, the feedback signal being received from a compensator of the power converter and being based on an output voltage of the power converter. A nonlinear gain block of the power converter controller receives the digital representation of the feedback signal and generates a transformed digital representation of the feedback signal using a nonlinear function. A switch control block of the power converter controller controls an on-time of a primary-side switch of the power converter based on the transformed digital representation of the feedback signal.

Abstract: An active clamp circuit includes an active clamp switch having a drain node and a source node, an active clamp capacitor coupled in a series combination with the active clamp switch, a delay circuit, and an active clamp controller circuit coupled to the active clamp switch and to the delay circuit. The active clamp controller circuit is configured to i) receive an active clamp switch voltage based on a voltage developed across the drain node and the source node of the active clamp switch, ii) enable the active clamp switch based on a voltage amplitude of the active clamp switch voltage, and iii) disable the active clamp switch based on a delay signal generated by the delay circuit.

Abstract: A quasi-resonant auto-tuning controller includes a zero-voltage crossing detection circuit and a valley tuning finite-state machine having a look-up table. The zero-voltage crossing detection circuit receives a reference voltage and receives an auxiliary signal from an auxiliary winding. The zero-voltage crossing detection circuit produces a comparison signal having pulses when the auxiliary signal is less than the reference voltage. The valley tuning finite-state machine produces a divided pulse width based on the comparison signal, stores the divided pulse width of each pulse in the look-up table, determines, from the comparison signal, that the auxiliary signal is less than the reference voltage, waits a time period corresponding to the divided pulse width stored in the look-up table if the auxiliary signal is less than the reference voltage, and produces a valley point signal after waiting the time period.

Abstract: A power converter controller includes a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a main switch, the target number of valleys corresponding to a desired off-time of the main switch, the fractional valley controller modulating an off-time of the main switch between two or more modulated off-times. The target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch. Each of the modulated off-times of the main switch corresponds to an integer number of valleys, and the two or more modulated off-times of the main switch has an average value that corresponds to the desired off-time.

Abstract: A switched-mode power controller includes a primary side controller circuit configured in a startup mode of operation to generate a fixed switching frequency pulse width modulation (PWM) signal with incrementing duty-ratio value. The PWM signal drives a main-switch that charges an inductive device with stored energy and discharges the stored energy into a capacitor on a secondary side to generate a power controller output voltage. Based on a comparison of the power controller output voltage with a reference voltage, the primary side controller circuit is configured to stop the incrementing of the duty-ratio of the PWM signal and begin a quasi-resonant mode of operation during which the primary side controller circuit reduces a number of valleys detected in one or more off-times of the main-switch in one or more respective main-switch switching periods.

Abstract: A quasi-resonant auto-tuning controller includes a zero-voltage crossing detection circuit and a valley tuning finite-state machine having a look-up table. The zero-voltage crossing detection circuit receives a reference voltage and receives an auxiliary signal from an auxiliary winding. The zero-voltage crossing detection circuit produces a comparison signal having pulses when the auxiliary signal is less than the reference voltage. The valley tuning finite-state machine produces a divided pulse width based on the comparison signal, stores the divided pulse width of each pulse in the look-up table, determines, from the comparison signal, that the auxiliary signal is less than the reference voltage, waits a time period corresponding to the divided pulse width stored in the look-up table if the auxiliary signal is less than the reference voltage, and produces a valley point signal after waiting the time period.

Abstract: The anti-windup circuit generally has a voltage clamping device in series with a current limiting device operatively connectable to the output current path of a feedback compensator; the feedback compensator being part of a switch-mode power supply (SMPS) having an input voltage source and a load and generating constrained control values required to generate control on-off actions for tight power regulation. The inclusion of the disclosed anti-windup circuit in an SMPS may lead to hardware based overvoltage protection, reduced overall size and faster response to load changes.

Abstract: A flyback converter includes a primary side circuit to receive an input voltage signal, a secondary side circuit to generate an output voltage signal using the input voltage signal, a synchronous rectifier switch, and a synchronous rectifier controller. The synchronous rectifier controller receives an attenuated drain-source voltage signal of the synchronous rectifier switch and the output voltage signal. The synchronous rectifier controller includes a threshold voltage generator to generate a first voltage signal using the output voltage signal, a first comparator to compare the attenuated drain-source voltage signal to the first voltage signal and, in response, generate a first comparison signal, and a second comparator to compare the attenuated drain-source voltage signal to a second voltage signal and, in response, generate a second comparison signal.

Abstract: A power converter includes an input side to receive an input voltage, and an output side to provide an output voltage, a main switch, a controller, a transformer having a primary winding that couples the main switch to the input side, an active clamp switch coupled to the input side by an active clamp capacitor, and an active clamp controller circuit. The active clamp controller circuit includes a sampling circuit to generate a sampled main switch voltage, a delay circuit to generate a delayed sampled main switch voltage, a voltage comparison circuit, and an active clamp switch controller circuit configured to i) enable the active clamp switch based on a first comparison between the sampled main switch voltage and the delayed sampled main switch voltage, and ii) disable the active clamp switch based on a second comparison between the sampled main switch voltage and the delayed sampled main switch voltage.

Abstract: A switched-mode power controller includes a primary side controller circuit configured in a startup mode of operation to generate a fixed switching frequency pulse width modulation (PWM) signal with incrementing duty-ratio value. The PWM signal drives a main-switch that charges an inductive device with stored energy and discharges the stored energy into a capacitor on a secondary side to generate a power controller output voltage. Based on a comparison of the power controller output voltage with a reference voltage, the primary side controller circuit is configured to stop the incrementing of the duty-ratio of the PWM signal and begin a quasi-resonant mode of operation during which the primary side controller circuit reduces a number of valleys detected in one or more off-times of the main-switch in one or more respective main-switch switching periods.

Abstract: The anti-windup circuit generally has a voltage clamping device in series with a current limiting device operatively connectable to the output current path of a feedback compensator; the feedback compensator being part of a switch-mode power supply (SMPS) having an input voltage source and a load and generating constrained control values required to generate control on-off actions for tight power regulation. The inclusion of the disclosed anti-windup circuit in an SMPS may lead to hardware based overvoltage protection, reduced overall size and faster response to load changes.

Abstract: A dual path and mode start-up circuit includes a high-voltage start-up circuit, an auxiliary start-up circuit, a capacitor, and a sensing circuit. The high-voltage start-up circuit has high-voltage input and output voltage nodes and is configurable to be operated in a first or second mode of operation. The auxiliary start-up circuit has auxiliary input and output voltage nodes. The auxiliary output voltage node, the high-voltage output voltage node, and the capacitor are in signal communication. The sensing circuit is configured to sense a voltage level at the capacitor and to configure the high-voltage start-up circuit to operate in the first mode of operation if the voltage level at the capacitor is less than a first threshold voltage level, and configure the high-voltage start-up circuit to operate in the second mode of operation if the voltage level at the capacitor is greater than a second threshold voltage level.

Abstract: An apparatus includes a high-pass filter circuit configured to receive a drain-source voltage from a drain node of a synchronous rectifier switch at a secondary-side of a power converter and to generate a filtered drain-source voltage using the received drain-source voltage. A current comparison circuit of the apparatus is configured to receive a current indicative of a current through the synchronous rectifier switch and to generate a current comparison signal using the received current. An auto-tuning controller of the apparatus is configured to turn the synchronous rectifier switch on upon determining a body diode conduction of the synchronous rectifier switch, commence an auto-tuned delay upon determining that the current through the synchronous rectifier switch has changed direction, turn the synchronous rectifier switch off upon expiration of the auto-tuned delay, and update, during a detection window of time, a duration of the auto-tuned delay based on the filtered drain-source voltage.

Abstract: An active clamp circuit includes an active clamp capacitor coupled in series with an active clamp switch and an active clamp controller circuit to receive an active clamp switch current that passes through the active clamp switch and to control the active clamp switch based on the received active clamp switch current. The active clamp controller circuit is configured to enable the active clamp switch based on a first amplitude comparison, the first amplitude comparison being based on the active clamp switch current. The active clamp controller circuit is configured to disable the active clamp switch based on a second amplitude comparison and a third amplitude comparison, the second amplitude comparison and the third amplitude comparison being based on the active clamp switch current.