Patents by Inventor Alexander Frey
Alexander Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260145929Abstract: A MEMS transducer includes a deflectable membrane where the deflectable membrane includes two first layers and a second layer arranged between the two first layers. The two first layers comprise low-stress silicon nitride, and the second layer comprises doped silicon.Type: ApplicationFiled: October 10, 2025Publication date: May 28, 2026Inventors: Abhiraj Basavanna, Alexander Frey, Hans-Jörg Timme, Marc Füldner
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Patent number: 12635548Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal; surface-activating the first hybrid interface layer and the second hybrid interface layer by particle bombardment; and bringing the surface-activated first hybrid interface layer and the surface-activated second hybrid interface layer into contact, such that the first and second insulators bond together and the first and second metals bond together at the same time.Type: GrantFiled: April 1, 2024Date of Patent: May 19, 2026Assignee: Infineon Technologies AGInventors: Alfred Sigl, Alexander Frey
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Patent number: 12628461Abstract: A passivation method for a passage opening of a wafer, at least having the steps of: providing a wafer having a top, a bottom and comprising a plurality of solar cell stacks, wherein each solar cell stack has a Ge substrate that forms the bottom of the wafer, a Ge sub-cell, at least two III-V sub-cells, in the named order, and at least one passage opening extending from the top to the bottom of the wafer, with a contiguous side wall and a circumference that is oval in cross section, and applying a dielectric insulating layer by means of chemical vapor deposition to the top of the wafer, the bottom of the wafer and the side wall of the passage opening.Type: GrantFiled: August 31, 2020Date of Patent: May 12, 2026Assignee: Azur Space Solar Power GmbHInventor: Alexander Frey
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Publication number: 20260061489Abstract: Disclosed is a method for controlling an energy input device of an additive manufacturing device. A beam bundle deflection center is assigned to each of the number of beam bundles from which this beam bundle is directed onto the build plane beam bundle deflection center is assigned a projection center corresponding to a perpendicular projection of the position of the beam bundle deflection center onto the build plane directions of the movement vectors of the number of beam bundles when scanning the trajectories are defined such that at each of the solidification points in this section the movement vector has an angle with respect to a connection vector from this solidification point to the projection center of the beam bundle used, which angle is smaller than a predetermined maximum angle ?1.Type: ApplicationFiled: November 7, 2025Publication date: March 5, 2026Inventors: Sarah Brandt, Alexander Frey
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Patent number: 12491562Abstract: Disclosed is a method for controlling an energy input device of an additive manufacturing device. A beam bundle deflection center is assigned to each of the number of beam bundles from which this beam bundle is directed onto the build plane. Each beam bundle deflection center is assigned a projection center corresponding to a perpendicular projection of the position of the beam bundle deflection center onto the build plane. The directions of the movement vectors of the number of beam bundles when scanning the trajectories are defined such that at each of the solidification points in this section the movement vector has an angle with respect to a connection vector from this solidification point to the projection center of the beam bundle used, which angle is smaller than a predetermined maximum angle ?1.Type: GrantFiled: February 17, 2021Date of Patent: December 9, 2025Assignee: EOS GmbH Electro Optical SystemsInventors: Sarah Brandt, Alexander Frey
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Publication number: 20250310700Abstract: In an embodiment a MEMS structure includes a back-plate structure, a support structure having a cavity, a membrane structure between the back-plate structure and the support structure, a first clamping structure having a first structured oxide layer between the support structure and the membrane structure, wherein an inner edge of the first clamping structure is laterally offset from an edge of the cavity, and wherein an offset of the first clamping structure forms a gap between the support structure and the membrane structure, and a second clamping structure having a second structured oxide layer and a first structured taper layer between the back-plate structure and the membrane structure, wherein the second structured oxide layer is arranged between the back-plate structure and the first structured taper layer, wherein an inner edge of the second structured oxide layer laterally extends over the cavity, and wherein the first structured taper layer is arranged between the second structured oxide layer.Type: ApplicationFiled: March 13, 2025Publication date: October 2, 2025Inventors: Abhiraj Basavanna, Hans-Jörg Timme, Alexander Frey, Marc Füldner, Konstantin Tkachuk
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Publication number: 20250270086Abstract: In an embodiment a semiconductor device includes a flexible element configured to convert a sound wave into a displacement, a layer spaced apart from and facing the flexible element and an anti-sticking element arranged between the flexible element and the layer and arranged on the flexible element or the layer, wherein the anti-sticking element is configured to prevent the flexible element and the layer from sticking together, wherein a surface of the anti-sticking element facing the other one of the flexible element or the layer comprises a recess, and wherein the recess has a depth of at least 10 nm.Type: ApplicationFiled: February 5, 2025Publication date: August 28, 2025Inventors: Hans-Jörg Timme, Alexander Frey, Jun Cheng Ooi, Markus Schuster, Abidin Güçlü Onaran, Abhiraj Basavanna, Konstantin Tkachuk, Marc Füldner
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Publication number: 20240274573Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal; surface-activating the first hybrid interface layer and the second hybrid interface layer by particle bombardment; and bringing the surface-activated first hybrid interface layer and the surface-activated second hybrid interface layer into contact, such that the first and second insulators bond together and the first and second metals bond together at the same time.Type: ApplicationFiled: April 1, 2024Publication date: August 15, 2024Inventors: Alfred Sigl, Alexander Frey
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Patent number: 11952888Abstract: A coupling element connectable to a string of one or more pipes, for example, a drill string of one or more pipes or drill pipes is provided. The coupling element is configured to excite, responsive to a data signal fed to the coupling element, an electromagnetic wave in the string. The coupling element comprises a feed portion at a first end of the coupling element, the feed portion to receive the data signal, a first electrically conductive portion extending from the feed portion towards a second end of the coupling element, the second end to be connected to the string for forming an electrically conductive connection between the first electrically conductive portion and the string, and a second electrically conductive portion extending from the feed portion towards the second end of the coupling element. The first and second electrically conductive portions are arranged so as to define a waveguide. The waveguide expands in a direction from the first end towards the second end.Type: GrantFiled: March 20, 2020Date of Patent: April 9, 2024Assignee: Herrenknecht AGInventors: Wilhelm Keusgen, Mathis Schmieder, Frederic Seng, Alexander Frey, Felix Weber
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Patent number: 11948912Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.Type: GrantFiled: February 1, 2023Date of Patent: April 2, 2024Assignee: Infineon Technologies AGInventors: Alfred Sigl, Alexander Frey
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Publication number: 20240105863Abstract: A stacked multi-junction solar cell with a front side contacted through the rear side and having a solar cell stack having a Ge substrate layer, a Ge subcell, and at least two III-V subcells, with a through contact opening, a front terminal contact, a rear terminal contact, an antireflection layer formed on a part of the front side of the multi-junction solar cell, a dielectric insulating layer, and a contact layer. The dielectric insulating layer covers the antireflection layer, an edge region of a top of the front terminal contact, a lateral surface of the through contact opening, and a region of the rear side of the solar cell stack adjacent to the through contact opening. The contact layer from a region of the top of the front terminal contact that is not covered by the dielectric insulating layer through the through contact opening to the rear side.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Applicant: AZUR SPACE Solar Power GmbHInventors: Wolfgang KOESTLER, Alexander FREY
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Publication number: 20240079515Abstract: A method for structuring an insulating layer on a semiconductor wafer includes providing a semiconductor wafer with a top, a bottom and includes multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which include the passage opening, and into the passage opening.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: AZUR SPACE Solar Power GmbHInventors: Alexander FREY, Benjamin HAGEDORN
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Patent number: 11881532Abstract: A stacked multi-junction solar cell with a front side contacted through the rear side and having a solar cell stack having a Ge substrate layer, a Ge subcell, and at least two III-V subcells, with a through contact opening, a front terminal contact, a rear terminal contact, an antireflection layer formed on a part of the front side of the multi-junction solar cell, a dielectric insulating layer, and a contact layer. The dielectric insulating layer covers the antireflection layer, an edge region of a top of the front terminal contact, a lateral surface of the through contact opening, and a region of the rear side of the solar cell stack adjacent to the through contact opening. The contact layer from a region of the top of the front terminal contact that is not covered by the dielectric insulating layer through the through contact opening to the rear side.Type: GrantFiled: November 23, 2020Date of Patent: January 23, 2024Assignee: AZUR SPACE Solar Power GmbHInventors: Wolfgang Koestler, Alexander Frey
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Publication number: 20240017986Abstract: A MEMS device comprises a first membrane structure having a reinforcement region formed from one piece of the first membrane structure, wherein the reinforcement region has a larger layer thickness than an adjoining region of the first membrane structure. The MEMS device includes an electrode structure, wherein the electrode structure is vertically spaced apart from the first membrane structure.Type: ApplicationFiled: July 14, 2023Publication date: January 18, 2024Inventors: Stefan Barzen, Alexander Frey, Matthias Friedrich Herrmann, Jun Cheng Ooi, Hans-Jörg Timme
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Patent number: 11830962Abstract: A method for structuring an insulating layer on a semiconductor wafer, at least comprising the steps of: Provision of a semiconductor wafer with a top, a bottom and comprising multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which comprises the passage opening, and into the passage opening.Type: GrantFiled: February 9, 2022Date of Patent: November 28, 2023Assignee: AZUR SPACE Solar Power GmbHInventors: Alexander Frey, Benjamin Hagedorn
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Publication number: 20230178512Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: Alfred Sigl, Alexander Frey
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Patent number: 11626531Abstract: A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material.Type: GrantFiled: August 24, 2018Date of Patent: April 11, 2023Assignee: OSRAM OLED GMBHInventors: Massimo Drago, Alexander Frey, Joachim Hertkorn, Ingrid Koslow
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Publication number: 20230077127Abstract: Disclosed is a method for controlling an energy input device of an additive manufacturing device. A beam bundle deflection center is assigned to each of the number of beam bundles from which this beam bundle is directed onto the build plane. Each beam bundle deflection center is assigned a projection center corresponding to a perpendicular projection of the position of the beam bundle deflection center onto the build plane. The directions of the movement vectors of the number of beam bundles when scanning the trajectories are defined such that at each of the solidification points in this section the movement vector has an angle with respect to a connection vector from this solidification point to the projection center of the beam bundle used, which angle is smaller than a predetermined maximum angle ?1.Type: ApplicationFiled: February 17, 2021Publication date: March 9, 2023Applicant: EOS GmbH Electro Optical SystemsInventors: Sarah Brandt, Alexander Frey
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Patent number: 11594515Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated by particle bombardment which is configured to remove atoms of the first hybrid interface layer and atoms of the second hybrid interface layer to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.Type: GrantFiled: November 3, 2021Date of Patent: February 28, 2023Assignee: Infineon Technologies AGInventors: Alfred Sigl, Alexander Frey
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Patent number: 11502224Abstract: A semiconductor body main include a III-V compound semiconductor material having a p-conductive region doped with a p-dopant. The p-conductive region may include at least one first section, one second section, and one third section. The second section may be arranged between the first and third sections. The second section may directly adjoin the first and third sections. An indium concentration of at least one of the sections differs from an indium concentration of the other two sections.Type: GrantFiled: June 14, 2018Date of Patent: November 15, 2022Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Ingrid Koslow, Massimo Drago, Joachim Hertkorn, Alexander Frey