Abstract: A circuit arrangement has a sensor electrode, a control circuit which is coupled to the sensor electrode via an input, and a current source which is coupled via a control input to a control output of the control circuit. The current source can be controlled by the control circuit. The control circuit is arranged so that if the current signal at its input is outside a predetermined current intensity range, the control circuit controls the current source so that the current source sets the electric current generated by it so that the electric current flowing into the input of the control circuit is brought to a predetermined current intensity value. Furthermore, the control circuit is set up in such a way that if the current signal at its input is within the predetermined current intensity range, the control circuit controls the current source so that the current source holds the electric current generated by it at the present value.

Abstract: Circuit arrangement having a sensor electrode, a first circuit unit, which is electrically coupled to the sensor electrode, and a second circuit unit, which has a first capacitor. The first circuit unit holds an electrical potential of the sensor electrode in a predetermined first reference range around a predetermined electrical desired potential by coupling the first capacitor and the sensor electrode such that there is a matching of their electrical potentials. If the second circuit unit detects the electrical potential of the first capacitor being outside a second reference range, the second circuit unit brings the first capacitor to a first electrical reference potential.

Abstract: A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones.

Abstract: Sensor arrangement, set up as an integrated circuit, having a substrate, at least three sensor electrodes arranged on the substrate such that, in an operating state in which an electrically conductive substance is introduced into the sensor arrangement, the sensor electrodes are coupled to one another by means of the electrically conductive substance, capture molecules immobilized on at least a portion of the sensor electrodes, wherein molecules to be detected can hybridize with the capture molecules, a control circuit for applying a first electrical signal to a selected sensor electrode and simultaneously applying a second electrical signal to at least two of the other sensor electrodes, the first electrical signal being a first temporally variable electrical signal and/or the second electrical signal being a second temporally variable electrical signal, a detection device, which is set up such that, in a first operating state, in which a reference liquid is introduced into the sensor arrangement, a referenc

Abstract: A system and method for providing multiple disk fault tolerance in an N-column by R-row logical representation of stored elements in an array of N independent disks, R minus 1 being less than N divided by a number of disk failures F, includes assigning each strip containing data to at least F different parity groups so that each strip containing data in a respective column is assigned to parity groups different than other strips containing data in the column. The method also includes calculating, for each parity group, a parity value corresponding to all of the strips assigned to the parity group. The method further includes storing each of the parity values in strips of different columns, so that none of the strips containing data in a column are assigned to a parity group for which the parity value for the parity group is stored in the column.

Abstract: In a first phase a first sensor signal, essentially comprising the current offset signal of the sensor, is applied to the input of an electronic circuit. The first sensor signal is fed to a first signal path and stored therein. In a second phase a second sensor signal, comprising the current offset signal and a time-dependent measured signal, is applied to the input and the stored first sensor signal is fed to the input by means of the first signal path, such that essentially the time dependent measured signal is fed by means of a second signal path coupled to the input.

Abstract: Circuit arrangement having a sensor electrode, a first circuit unit, which is electrically coupled to the sensor electrode, and a second circuit unit, which has a first capacitor. The first circuit unit holds an electrical potential of the sensor electrode in a predetermined first reference range around a predetermined electrical desired potential by coupling the first capacitor and the sensor electrode such that there is a matching of their electrical potentials. If the second circuit unit detects the electrical potential of the first capacitor being outside a second reference range, the second circuit unit brings the first capacitor to a first electrical reference potential.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Abstract: A biochip arrangement, comprising a substrate, at least one sensor arranged on or in the substrate, and an electrically conductive permeation layer, arranged at a predetermined distance other than zero from the surface of the substrate and to which an electric voltage can be applied. As a result of the electrically conductive permeation layer being arranged at a distance other than zero from the surface of the substrate, there is no need for the permeation layer to be integrated on or in the chip. Therefore, production of the biochip arrangement eliminates the heretofore required method step of securing the permeation layer to the chip. This reducing cost and time required to produce the arrangement. The physical separation of the permeation layer from the substrate also brings with it the further advantage that the permeation layer does not take up any area on the substrate surface.

Abstract: A description is given of a DRAM memory (10) having a number of DRAM memory cells (15) which each form one or more memory cell arrays (11). Each memory cell (15) is connected to a bit line (12) and a reference bit line (13), respectively. The individual bit lines (12; 13) are furthermore connected to at least one read/write amplifier (30) according to the invention. In order that the read/write amplifier circuit (30) can perform the tasks intended for it with high evaluation reliability and speed in conjunction with the smallest possible space requirement, the invention specifies a space-saving sense amplifier scheme in which the read/write amplifier (30) has a first read/write amplifier element (40) and a second read/write amplifier element (50) separate therefrom, the individual amplifier components (41, 42, 43, 51, 54) being divided between the two read/write amplifier elements (40, 50).

Abstract: The invention relates to a biosensor that is provided with a first electrode having a first holding area and a second electrode having a second holding area for holding probe molecules which can bind macromolecular biopolymers to be detected. The first electrode and the second electrode are arranged in relation to one another in such a way that essentially unbent field lines of a generated electric field can be embodied between said electrodes.

Abstract: In a first phase a first sensor signal, essentially comprising the current offset signal of the sensor, is applied to the input of an electronic circuit. The first sensor signal is fed to a first signal path and stored therein. In a second phase a second sensor signal, comprising the current offset signal and a time-dependent measured signal, is applied to the input and the stored first sensor signal is fed to the input by means of the first signal path, such that essentially the time dependent measured signal is fed by means of a second signal path coupled to the input.

Abstract: The invention relates to a biosensor chip that is provided with a first electrode and a second electrode. The first electrode is provided with a holding area for holding probe molecules which can bind macromolecular biopolymers. The invention also relates to an integrated electric differentiating circuit by means of which an electric current can be detected and can be differentiated according to time, whereby said current is generated during a reduction/oxidation recycling procedure.

Abstract: The invention relates to a first electrode that is provided with a holding area for holding probe molecules which can bind macromolecular biopolymers. The first electrode and/or a second electrode is/are divided into a plurality of electrode segments that are electrically insulated from one another. The randomly selected electrode segments, independently from one another, can be electrically coupled in such a way that an effective electrode surface can be adjusted in the size thereof according to the selected electrode segments.

Abstract: A description is given of a sense amplifier subcircuit (10), for example an N latch section or a P latch section, for a DRAM memory for amplifying voltage signals read from a bit line (50), having at least two evaluation transistors (20; 30), the gate (21) of one evaluation transistor (20) being connected or connectable to at least one bit line (50) and the gate (31) of another evaluation transistor (30) being connected or connectable to at least one reference bit line (51) and the drains (23, 33) of the evaluation transistors (20; 30) being connected or connectable to the bit lines (51, 50) and the sources (22, 32) of the evaluation transistors (20; 30) being connected or connectable to a (NCS/PCS) lead (11).

Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another.

Abstract: A description is given of a DRAM memory (10) having a number of DRAM memory cells (15) which each form one or more memory cell arrays (11). Each memory cell (15) is connected to a bit line (12) and a reference bit line (13), respectively. The individual bit lines (12; 13) are furthermore connected to at least one read/write amplifier (30) according to the invention. In order that the read/write amplifier circuit (30) can perform the tasks intended for it with high evaluation reliability and speed in conjunction with the smallest possible space requirement, the invention specifies a space-saving sense amplifier scheme in which the read/write amplifier (30) has a first read/write amplifier element (40) and a second read/write amplifier element (50) separate therefrom, the individual amplifier components (41, 42, 43, 51, 54) being divided between the two read/write amplifier elements (40, 50).

Abstract: A description is given of a sense amplifier subcircuit (10), for example an N latch section or a P latch section, for a DRAM memory for amplifying voltage signals read from a bit line (50), having at least two evaluation transistors (20; 30), the gate (21) of one evaluation transistor (20) being connected or connectable to at least one bit line (50) and the gate (31) of another evaluation transistor (30) being connected or connectable to at least one reference bit line (51) and the drains (23, 33) of the evaluation transistors (20; 30) being connected or connectable to the bit lines (51, 50) and the sources (22, 32) of the evaluation transistors (20; 30) being connected or connectable to a (NCS/PCS) lead (11). According to the invention, at least one of the evaluation transistors (20; 30) is designed in such a way that its threshold voltage changes dynamically during the evaluation operation by virtue of the change in the gate voltage being coupled to a change in the body voltage.

Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.