Abstract: A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Abstract: A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Abstract: A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.

Abstract: Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed.

Abstract: A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

Abstract: A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

Abstract: A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Abstract: A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

Abstract: Full-duplex communications over a single-wire bus is described in the present disclosure. In embodiments disclosed herein, a master circuit and a slave circuit(s) are able to communicate forward (master to slave) bus telegrams and reverse (slave to master) bus telegrams concurrently over a single-wire bus consisting of one wire. Specifically, the master circuit is configured to modulate the forward bus telegrams based on voltage pulse-width modulation (PWM), while the slave circuit(s) is configured to modulate the reverse bus telegrams based on current variations. In addition, the slave circuit(s) is further configured to harvest power from the master circuit concurrent to receiving the forward bus telegrams and sending the reverse bus telegrams. By supporting full-duplex communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device wherein the single-wire bus is deployed.

Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: A single-wire bus apparatus that includes a bus slave circuit(s) is provided. The bus slave circuit(s) can receive a unicast, a multicast, and/or a broadcast command sequence over a single-wire bus. In embodiments disclosed herein, the bus slave circuit(s) can be configured to determine whether to respond to a received multicast or broadcast command sequence based on a predefined response policy. As such, the single-wire bus apparatus can be configured to mix and match a legacy slave circuit(s), which always responds to the received multicast or broadcast command sequence, with an enhanced slave circuit(s) that can decide whether to respond to the received multicast or broadcast command sequence based on the predefined response policy. As a result, it is possible to improve design and implementation flexibility, such as supporting more bus slave circuits per port.

Abstract: Full-duplex communications over a single-wire bus is described in the present disclosure. In embodiments disclosed herein, a master circuit and a slave circuit(s) are able to communicate forward (master to slave) bus telegrams and reverse (slave to master) bus telegrams concurrently over a single-wire bus consisting of one wire. Specifically, the master circuit is configured to modulate the forward bus telegrams based on voltage pulse-width modulation (PWM), while the slave circuit(s) is configured to modulate the reverse bus telegrams based on current variations. In addition, the slave circuit(s) is further configured to harvest power from the master circuit concurrent to receiving the forward bus telegrams and sending the reverse bus telegrams. By supporting full-duplex communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device wherein the single-wire bus is deployed.

Abstract: A single-wire bus apparatus that includes a bus slave circuit(s) is provided. The bus slave circuit(s) can receive a unicast, a multicast, and/or a broadcast command sequence over a single-wire bus. In embodiments disclosed herein, the bus slave circuit(s) can be configured to determine whether to respond to a received multicast or broadcast command sequence based on a predefined response policy. As such, the single-wire bus apparatus can be configured to mix and match a legacy slave circuit(s), which always responds to the received multicast or broadcast command sequence, with an enhanced slave circuit(s) that can decide whether to respond to the received multicast or broadcast command sequence based on the predefined response policy. As a result, it is possible to improve design and implementation flexibility, such as supporting more bus slave circuits per port.

Abstract: An envelope tracking (ET) amplifier apparatus is provided. The ET amplifier apparatus includes an ET integrated circuit (ETIC) and a distributed ETIC (DETIC) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority, respectively. The ETIC and the DETIC can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state configured to permit bus contention. In a non-limiting example, a winner for the single-wire bus is a peer device having a highest bus access priority between the ETIC and the DETIC. In this regard, each of the ETIC and the DETIC can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional peer-to-peer (P2P) bus architecture capable of supporting more application and/or deployment scenarios.

Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.

Abstract: A hybrid bus hub circuit and related apparatus are provided. The bus hub circuit can be configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses of different types. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). The hybrid bus hub circuit can be configured to selectively activate an auxiliary bus(es) for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: A hybrid bus apparatus is provided. The hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple a master(s) with one or more auxiliary slaves via heterogeneous communication buses. The hybrid bus bridge circuit and the auxiliary slaves are associated with respective unique slave identifications (USIDs). The master(s) can only support a fixed number of the USIDs, and thus a fixed number of the auxiliary slaves. The hybrid bus bridge circuit is configured to opportunistically mask some or all of the auxiliary slaves such that the respective USIDs associated with the masked auxiliary slaves can be reused by the master(s) to support additional slaves. As such, it may be possible to extend the capability of the master(s) to support more slaves than the fixed number of USIDs the master(s) can provide, thus enabling flexible heterogeneous bus deployment in an electronic device incorporating the hybrid bus apparatus.

Abstract: A single-wire peer-to-peer (P2P) bus apparatus is provided. The single-wire P2P bus apparatus includes a first peer device and a second peer device(s) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority(s), respectively. Any of the first peer device and the second peer device(s) can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state. A winner for the single-wire bus may be a peer device having a highest bus access priority among those peer devices asserting the bus contention indication(s). In this regard, any peer device on the single-wire bus can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional P2P bus architecture capable of supporting more application and/or deployment scenarios.

Abstract: A single-wire bus (SuBUS) slave circuit is provided. The SuBUS slave circuit is coupled to a SuBUS bridge circuit via a SuBUS and can be configured to perform a slave task that may block communication on the SuBUS. Notably, the SuBUS slave circuit may not be equipped with an accurate timing reference source that can determine a precise timing for terminating the slave task and unblock the SuBUS. Instead, the SuBUS slave circuit is configured to terminate the slave task and unblock the SuBUS based on a self-determined slave free-running-oscillator count derived from a start-of-sequence training sequence that precedes any SuBUS telegram of a predefined SuBUS operation, even though the SuBUS operation is totally unrelated to the slave task. As such, it may be possible to eliminate the accurate timing reference source from the SuBUS slave circuit, thus helping to reduce cost and current drain in the SuBUS slave circuit.

Abstract: A multi-radio access technology (RAT) circuit is provided. The multi-RAT circuit includes a radio frequency (RF) circuit(s) coupled to an interconnect medium(s). The RF circuit(s) includes a power head circuit configured to receive a local oscillation (LO) pilot and an RF signal via the interconnect medium(s). The power head circuit generates an LO signal based on the LO pilot without requiring a synthesizer. Accordingly, the power head circuit modulates the RF signal to a carrier band based on the LO signal for transmission in a millimeter wave (mmWave) spectrum. By generating the LO signal and modulating the RF signal to the carrier band in the power head circuit, it may be possible to minimize attenuation and/or interference to the RF signal. Further, it may also be possible to share the interconnect medium(s) with existing RATs, thus helping to reduce size, power, and cost impacts associated with supporting an mmWave RAT.