Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: A communications system includes a single wire communications bus and a plurality of slave devices, each of the slave devices associated with a common slave identifier. The single wire communications bus is configured to receive a message comprising data, a slave identifier, and a register map address. A respective one of the plurality of slave devices selectively responds to the message if the slave identifier in the message is the same as the common slave identifier associated with the respective one of the plurality of slave devices and the register map address in the message is the same as the register map address associated with the respective one of the plurality of slave devices.

Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: A power management circuit and related radio frequency (RF) front-end circuit are provided. In examples discussed herein, a power management circuit can be incorporated into an RF front-end circuit to support RF beamforming in millimeter wave spectrum(s). In this regard, the power management circuit is configured to generate multiple output voltages to drive multiple power amplifier subarrays in the RF front-end circuit. More specifically, the power management circuit is configured to generate the output voltages based on a voltage scaling factor(s) such that each of the output voltages corresponds proportionally to a battery voltage received by the power management circuit. As such, the output voltages can be dynamically controlled based on the voltage scaling factor(s) to maximize operating efficiency of the power amplifier subarrays. As a result, it is possible to reduce heat dissipation of the power amplifier subarrays and improve overall thermal performance of the RF front-end circuit.

Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each include a plurality of pins. The first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

Abstract: A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each include a plurality of pins. The first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

Abstract: An outphasing power management circuit for radio frequency (RF) beamforming is disclosed. The outphasing power management circuit includes a first outphasing amplifier branch consisting of a plurality of first power amplifiers and a second outphasing amplifier branch consisting of a plurality of second power amplifiers. A controller operates the first outphasing amplifier branch and the second outphasing amplifier branch as a pair of outphasing power amplifiers. The first outphasing amplifier branch generates a plurality of first output signals, and the second outphasing amplifier branch generates a plurality of second output signals. The first output signals and the second output signals are transmitted in an RF beam without being combined. As such, it is possible to support RF beamforming with a reduced number of power amplifiers and/or direct current (DC) to DC converters, thus helping to improve efficiency and reduce cost.

Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.

Abstract: An outphasing power management circuit for radio frequency (RF) beamforming is disclosed. The outphasing power management circuit includes a first outphasing amplifier branch consisting of a plurality of first power amplifiers and a second outphasing amplifier branch consisting of a plurality of second power amplifiers. A controller operates the first outphasing amplifier branch and the second outphasing amplifier branch as a pair of outphasing power amplifiers. The first outphasing amplifier branch generates a plurality of first output signals, and the second outphasing amplifier branch generates a plurality of second output signals. The first output signals and the second output signals are transmitted in an RF beam without being combined. As such, it is possible to support RF beamforming with a reduced number of power amplifiers and/or direct current (DC) to DC converters, thus helping to improve efficiency and reduce cost.

Abstract: An apparatus for a multiple-input multiple-output (MIMO) architecture is disclosed. The apparatus includes a first splitter-combiner (S-C) having a first transmission line port, a first transmit (TX) port, and a first receive (RX) port. Also included is a first N-plexer having a first power amplifier (PA) input, a first RX output, and a first antenna output for coupling to a first antenna. A first PA is coupled between the first TX port and the PA input, wherein the first RX output is coupled to the first RX port.