Abstract: A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each include a plurality of pins. The first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

Abstract: A communications system includes a single wire communications bus and a plurality of slave devices, each of the slave devices associated with a common slave identifier. The single wire communications bus is configured to receive a message comprising data, a slave identifier, and a register map address. A respective one of the plurality of slave devices selectively responds to the message if the slave identifier in the message is the same as the common slave identifier associated with the respective one of the plurality of slave devices and the register map address in the message is the same as the register map address associated with the respective one of the plurality of slave devices.

Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.

Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.

Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.

Abstract: Antenna array calibration for wireless charging is disclosed. A wireless charging system is provided and configured to calibrate antenna elements in a wireless charging station based on a feedback signal provided by a wireless charging device. The antenna elements in the wireless charging station transmit wireless radio frequency (RF) charging signals to the wireless charging device. The wireless charging device provides the feedback signal to the wireless charging station to indicate total RF power in the wireless RF charging signals. The wireless charging station is configured to adjust transmitter phases associated with the antenna elements based on the feedback signal until the total RF power in the wireless RF charging signals is maximized. By calibrating the antenna elements based on the feedback signal, it is possible to achieve phase coherency among the antenna elements without requiring factory calibration.

Abstract: The exemplary embodiments include a radio frequency antenna switch configured to reject harmonic frequencies. In addition, the harmonic-rejected radio frequencies of the radio frequency antenna switch may be tuned by use of a capacitor array. The capacitor array may be configured with fuse elements or by control logic.

Abstract: The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.

Abstract: An apparatus for a multiple-input multiple-output (MIMO) architecture is disclosed. The apparatus includes a first splitter-combiner (S-C) having a first transmission line port, a first transmit (TX) port, and a first receive (RX) port. Also included is a first N-plexer having a first power amplifier (PA) input, a first RX output, and a first antenna output for coupling to a first antenna. A first PA is coupled between the first TX port and the PA input, wherein the first RX output is coupled to the first RX port.

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract: Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier.

Abstract: Aspects disclosed in the detailed description include an antenna on a device assembly. A device assembly includes a silicon device layer having at least one antenna. The device assembly also includes a polymer substrate that is formed with insulating material that does not interfere with the at least one antenna in the silicon device layer. As a result, it is unnecessary to shield the at least one antenna from the polymer substrate, thus allowing radio frequency (RF) signals radiating from the at least one antenna to pass through the polymer substrate.

Abstract: Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.

Abstract: Antenna array calibration for wireless charging is disclosed. A wireless charging system is provided and configured to calibrate antenna elements in a wireless charging station based on a feedback signal provided by a wireless charging device. The antenna elements in the wireless charging station transmit wireless radio frequency (RF) charging signals to the wireless charging device. The wireless charging device provides the feedback signal to the wireless charging station to indicate total RF power in the wireless RF charging signals. The wireless charging station is configured to adjust transmitter phases associated with the antenna elements based on the feedback signal until the total RF power in the wireless RF charging signals is maximized. By calibrating the antenna elements based on the feedback signal, it is possible to achieve phase coherency among the antenna elements without requiring factory calibration.

Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA.

Abstract: The present invention relates to estimating a battery current supplied from a battery to a switching power supply, which provides a regulated output signal to a load, based on a switching power supply current in the switching power supply, and then controlling the regulated output signal to limit the battery current to within an acceptable threshold. The switching power supply current may be provided by one or more switching elements in the switching power supply. The switching elements may be mirrored to provide a mirrored switching power supply current, which is used to estimate the battery current. The estimated battery current may include an estimated average battery current, an estimated instantaneous battery current, or both.

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.