Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

Abstract: An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

Abstract: A method for power amplifier (PA) calibration for an envelope tracking system of a wireless device is disclosed. The method involves measuring an output power of a PA that is a part under test (PUT) at a predetermined input power. Another step includes calculating a gain equal to the output power of the PA divided by the predetermined input power. A next step involves calculating a gain correction by subtracting the calculated gain from a desired gain. Other steps include determining an expected supply voltage for the PA at the desired gain using the gain correction applied to a nominal curve of gain versus PA supply voltage, and then storing the expected supply voltage for the PA versus input power in memory.

Abstract: The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.

Abstract: Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.

Abstract: In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system.

Abstract: A circuit and method for a saturation correction of a power amplifier (PA) is provided in order to maintain a desirable switching spectrum. The circuit includes a closed loop system that is responsive to a dynamic PA control signal known as VRAMP. The method samples a detector voltage that represents the output of the PA at the maximum voltage level of VRAMP. The sampled detector voltage is then reduced by a predetermined amount and applied as a fixed voltage PA control signal in the place of VRAMP. As a result, the closed loop system responds to the fixed voltage PA control signal to bring the PA out of saturation before VRAMP can begin a voltage decrease. Once the VRAMP voltage decreases, VRAMP is reapplied as a dynamic PA control signal in place of the fixed voltage control signal.

Abstract: The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA and a first-second PA, and a second PA block having a second-first PA and a second-second PA. First and second modulated switchers are adapted to selectively supply power to the first-first PA and the second-first PA, and to supply power to the first-second PA and the second-second PA, respectively. The first and second modulated switchers have a modulation bandwidth of at least 20 MHz and are both suitable for envelope tracking modulation. A control system is adapted to selectively enable and disable the first-first PA, first-second PA, the second-first PA, and the second-second PA. First and second switches are responsive to control signals to route carriers and received signals between first and second antennas depending upon a selectable mode of operation such as intra-band or inter-band operation.

Abstract: An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.

Abstract: The present disclosure relates to RF circuitry having delay locked loop (DLL) circuitry that may be used to measure amplitude modulation-to-phase modulation (AMPM) distortion of an RF power amplifier during factory calibration or during real time operation of the RF circuitry. During a calibration mode, the DLL circuitry may be calibrated using a reference clock signal. During a phase measurement mode, the DLL circuitry may use the reference clock signal, which is representative of an RF input signal to the RF power amplifier, and a feedback signal, which is representative of an RF output signal from the RF power amplifier, to measure a phase difference between the RF input signal and the RF output signal. By measuring the phase difference at different amplitudes of the RF output signal, the AMPM distortion of the RF power amplifier may be determined and used to correct for the AMPM distortion.

Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA.

Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

Abstract: A front end radio architecture (FERA) is disclosed that includes a transmitter block coupled to a power amplifier (PA) via first and second input terminals. A first split-band duplexer is coupled to a first output terminal of the PA and a second split-band duplexer is coupled to a second output terminal of the PA. The PA includes a first amplifier cell and a second amplifier cell that when coupled to the first and second split-band duplexers makes up first and second transmitter chains. Only one of the first and the second transmitter chains is active when a first carrier and a second carrier have a frequency offset that is less than an associated half duplex frequency within a same split-band duplex band, thus preventing third order inter-modulation (IMD) products from falling within an associated receive channel. Otherwise, the first and the second transmitter chains are both active.

Abstract: An over-voltage detection and correction system for a transmitter of a mobile terminal that accounts for battery droop during a transmit burst is provided. In general, prior to ramp-up for a first transmit burst, a voltage of the battery of the mobile terminal at a no-load condition is measured. After ramp-up for the transmit burst, the voltage of the battery is measured at full-load, and a current provided to a power amplifier of the transmitter at full-load is detected. Based on the measured voltage of the battery at no-load, the measured voltage of the battery at full-load, and the detected current provided to the power amplifier at full-load, a resistance of the battery is determined. The resistance of the battery is thereafter used to compensate for battery droop during over-voltage detection and correction for one or more subsequent transmit bursts.

Abstract: The present disclosure relates to multi-mode RF circuitry using a single IQ modulator topology that may support different communication standards, including enhanced data rates for global system for mobile communications evolution (EDGE) and EDGE evolution by dividing certain modulation functions between a frequency synthesizer and an IQ modulator. Specifically, during a standard modulation mode, which may be used to support many communications standards, the frequency synthesizer provides an un-modulated RF carrier signal to the IQ modulator, which either phase modulates or phase and amplitude modulates the un-modulated RF carrier signal to provide a standard modulated RF signal.

Abstract: A system and method for providing a polarization feedback linearization to correct a non-linear amplitude error of an amplitude and phase detector or polar detector is disclosed. The method involves correcting a non-linear phase error of an amplitude detector via a look up table (LUT) that is driven by a radio frequency (RF) signal. The LUT provides values that are usable to correct an RF output that is a function of the RF output signal and is not a function of a device that incorporates the open loop modulation system of the present disclosure. Specifically, a detection of the corrected RF output amplitude is usable to drive a phase correction so that the RF output with corrected phase is a function of the RF output alone and not a function of a system or circuit that generates the RF output signal.