Abstract: A method is provided for calibrating Amplitude Modulation to Phase Modulation (AM/PM) predistortion coefficients for a polynomial used to compensate for AM/PM distortion of a power amplifier in the transmit chain of a mobile terminal. In general, the power amplifier is controlled by a variable supply voltage, which is generated based on an adjustable power control signal. After the power amplifier is placed in the mobile terminal, a predetermined data pattern is transmitted in a transmit burst. During the transmit burst, the variable supply voltage is changed from a first value to a second value, and a resultant phase shift in the radio frequency output signal provided by the mobile terminal is measured. Based on the phase shift, one of numerous predetermined sets of AM/PM predistortion coefficients is selected as the AM/PM coefficients for the mobile terminal.

Abstract: A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.

Abstract: A system and method for detecting and correcting excess current in a power amplifier in a transmit chain of a mobile terminal are provided. Over current detection and correction circuitry compares a current detection signal indicative of an output current of the power amplifier to a maximum current ramp during ramp-up for a transmit burst. If the current detection signal exceeds the maximum current ramp, then a power control signal controlling a supply voltage provided to the power amplifier circuitry is reduced, thereby reducing the output power and output current. Over voltage detection and correction circuitry compares a voltage detection signal indicative of an output voltage of the power amplifier to a maximum voltage ramp during ramp-up for the transmit burst. If the voltage detection signal exceeds the maximum voltage ramp, then the power control signal is reduced.

Abstract: A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.

Abstract: A modulation system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The modulation system includes a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition, a timing signal triggers ramp-down of an output power of a power amplifier amplifying modulated data for the first transmit burst. Upon receiving the timing signal, the data interface proceeds to provide a current symbol of data for the first transmit burst. Upon completion of the current symbol, the data interface delays data for a second transmit burst by a variable delay time prior to providing the data for the second transmit burst to the second modulation circuitry, and the second modulation circuitry is reset. Accordingly, a glitch caused by resetting the second modulation circuitry occurs before ramp-up for the second transmit burst.

Abstract: A system is provided for correcting an output power of a power amplifier in a transmit chain of a mobile terminal. In one embodiment, the system includes output power correction circuitry that corrects the output power of the power amplifier during ramp-up for a transmit burst. The output power of the power amplifier is controlled based on a power control signal, which is provided by combining an amplitude component of a modulated signal and a corrected ramping signal provided by the output power correction circuitry. In general, a power amplifier ramp generator provides a ramping signal. The ramping signal is converted to a desired output power signal, which is subtracted from a detected output power signal to provide an error signal. The error signal is integrated to provide an adjustment signal, which is combined with an ideal ramping signal to provide the corrected ramping signal.

Abstract: A system and method for performing DC offset correction in a wireless communication receiver during “dead time” are provided. The receiver includes amplifier circuitry that amplifies a received radio frequency (RF) signal, downconversion circuitry that downconverts the received RF signal to provide a downconverted signal, digitization circuitry that digitizes the downconverted signal to provide a digital signal, and digital DC offset correction circuitry enabled during the dead time when there should be no DC content in the downconverted signal. In operation, the digital DC offset correction circuitry detects a DC offset of the digital signal and subtracts the DC offset from the digital signal.

Abstract: A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.

Abstract: A system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The system includes a modulation system having a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition between a first transmit burst in the first modulation format and a second transmit burst in the second modulation format, the data interface receives a timing signal signifying a start of data for the second transmit burst. In response to the timing signal, the second modulation circuitry resets, and the data interface delays the data for the second transmit burst by a modulator delay time. By delaying the data for the second transmit burst, a glitch caused by resetting the second modulation circuitry arrives at the output of the second modulation circuitry prior to the data for the second transmit burst.

Abstract: The present invention provides a receiver frontend that eliminates static and dynamic DC errors and has improved second order intermodulation distortion (IMD2) performance. The receiver frontend includes a first mixer that multiplies a received signal and a first local oscillator (LO) signal to produce an intermediate frequency (IF) signal. A second mixer multiplies the IF signal and a second LO signal to produce an output signal. A first divider circuit divides a reference signal from a reference oscillator by a first divisor N to produce the first LO signal, and a second divider circuit divides the reference signal by a second divisor M to produce the second LO signal. Preferably, the first and second divisors N and M are each integers greater than one (1), and the second divisor M is not an integer multiple of the first divisor N.

Abstract: A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

Abstract: A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

Abstract: A receiver performs DC offset correction by preliminarily using an unused LNA with a terminating resistance to determine a base level DC offset. Once the DC offset is determined, a DC offset correction may be calculated and applied to an active LNA output. When determining the DC offset, the active LNA is disabled.

Abstract: A polar modulator creates an amplitude signal and a frequency signal and digitally adjusts the signals so that the frequency and amplitude signals arrive at the power amplifier at the appropriate times. A digital predistortion filter is applied to the frequency signal. The frequency signal is then provided to a single port of a fractional N divider in a phase locked loop. The output of the phase locked loop drives an input of the power amplifier while the amplitude signal is converted to an analog signal and controls the power supply input of the power amplifier.

Abstract: The present invention provides a dummy low noise amplifier (LNA) and an associated resistive network. Prior to DC offset correction, the primary LNAs are deactivated and the antenna is decoupled from the receive path leading to the inputs of the primary LNAs. A resistance is selected to provide a load at the input of the dummy LNA, wherein the load emulates the input load resistance seen by the primary LNA, which will be used to receive the incoming signal. Thus, the output of the dummy LNA emulates the performance of the primary LNA used to receive the incoming signal to allow accurate DC offset correction.

Abstract: A transmitter includes a polar modulator that creates phase and amplitude signals which in turn drive a power amplifier. To compensate for AM to PM conversion of the amplitude signal into the amplified signal, a compensation signal is generated from the amplitude signal and combined with the phase signal such that when amplified, the compensation signal cancels the AM to PM conversion. The compensation signal may have an offset term, a linear term, a quadratic term, and a cubic term. A second embodiment comprises a technique by which AM to AM conversion may concurrently be addressed using a second compensation signal.

Abstract: A transmitter includes a polar converter to generate an amplitude signal and a phase signal, which in turn is converted to a frequency signal. The amplitude signal is directed to a compensator and a compensation signal is generated. The compensation signal is combined with the amplitude signal and the combined signal is presented to the power amplifier. The AM to AM conversion is reduced such that the output signal of the power amplifier contains substantially no spurious components.

Abstract: A polar modulator creates an amplitude signal and a frequency signal and digitally adjusts the signals so that the frequency and amplitude signals arrive at the power amplifier at the appropriate times. A digital predistortion filter is applied to the frequency signal. The frequency signal is then provided to a single port of a fractional N divider in a phase locked loop. The output of the phase locked loop drives an input of the power amplifier while the amplitude signal is converted to an analog signal and controls the power supply input of the power amplifier.

Abstract: The present invention provides a dummy low noise amplifier (LNA) and an associated resistive network. Prior to DC offset correction, the primary LNAs are deactivated and the antenna is decoupled from the receive path leading to the inputs of the primary LNAs. A resistance is selected to provide a load at the input of the dummy LNA, wherein the load emulates the input load resistance seen by the primary LNA, which will be used to receive the incoming signal. Thus, the output of the dummy LNA emulates the performance of the primary LNA used to receive the incoming signal to allow accurate DC offset correction.

Abstract: A portable radio communication device (303) includes power control circuitry (315) for monitoring the voltage level incoming from a battery (317), and provides power to the rest of the radio communication device (303). The power control circuitry (315) includes a boost regulator (407) that is used to generate an internal reference signal for use throughout the radio communication device including an analog to digital converter (ADC) for digitizing the battery voltage for use by the power control circuitry (315). The power control circuitry (315) compares the digitized battery voltage to thresholds to control power to the remainder of the radio communication device (303). Additionally, a secondary comparator (413) is provided to prevent damage to the battery and radio communication device circuitry. The secondary comparator uses multiple undervoltage thresholds depending upon the power state of the radio communication device (303).