Patents by Inventor Ali Khakifirooz

Ali Khakifirooz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937863
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10923622
    Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a first color nanowire LED, a second color nanowire LED, the second color different than the first color, and a pair of third color nanowire LEDs, the third color different than the first and second colors. A continuous insulating material layer ius laterally surrounding the first color nanowire LED, the second color nanowire LED, and the pair of third color nanowire LEDs.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi, Ali Khakifirooz
  • Patent number: 10903208
    Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
  • Patent number: 10896976
    Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
  • Patent number: 10892364
    Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
  • Patent number: 10886385
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Publication number: 20200395403
    Abstract: Micro light-emitting diode displays and methods of fabricating micro LED displays are described. In an example, a micro light emitting diode pixel structure includes a plurality of micro light emitting diode devices in a dielectric layer. A transparent conducting oxide layer is above the dielectric layer. A color conversion device (CCD) is above the transparent conducting oxide layer and over one of the plurality of micro light emitting diode devices.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Khaled AHMED, Anup PANCHOLI, Ali KHAKIFIROOZ
  • Patent number: 10845609
    Abstract: Diffractive optical elements for wide field-of-view virtual reality devices and methods of manufacturing the same are disclosed. An example apparatus includes a substrate and a thin film stack including alternating layers of a first material and a second material. The thin film stack defines an annular protrusion. The annular protrusion has a stair-like profile. Top surfaces of separate ones of steps in the stair-like profile correspond to top surfaces of separate ones of the layers of the second material.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Ali Khakifirooz, Prashant Majhi, Kunjal Parikh
  • Patent number: 10832766
    Abstract: An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Ali Khakifirooz, Pranav Kalavade, Uday Chandrasekhar, Trupti Bemalkhedkar, Chang Wan Ha
  • Patent number: 10811410
    Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 20, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10734499
    Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 10720528
    Abstract: A semiconductor structure is provided that includes a fin stack structure of, from bottom to top, a first semiconductor material fin portion, an insulator fin portion and a second semiconductor material fin portion. The first semiconductor material fin portion can be used as a first device region in which a first conductivity-type device (e.g., n-FET or p-FET) can be formed, while the second semiconductor material fin portion can be used as a second device region in which a second conductivity-type device (e.g., n-FET or p-FET), which is opposite the first conductivity-type device, can be formed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10714570
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10707332
    Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo
  • Publication number: 20200191746
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 18, 2020
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10679939
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10658513
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Publication number: 20200152622
    Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
  • Publication number: 20200135284
    Abstract: An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.
    Type: Application
    Filed: December 26, 2019
    Publication date: April 30, 2020
    Inventors: Justin R. DAYACAP, Shantanu R. RAJWADE, Kyung Jean YOON, Ali KHAKIFIROOZ, David J. PELSTER, Yogesh B. WAKCHAURE, Xin GUO
  • Patent number: 10629743
    Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 21, 2020
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie