Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.

Abstract: A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed.

Abstract: A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Abstract: A memory device is designed to store data in multilevel storage cells (MLC storage cells). The memory device includes a controller that dynamically writes data to the storage cells according to a first MLC density or a second MLC density. The second density is less dense than the first density. For example, the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

Abstract: A method performed by a non volatile memory is described. The method includes receiving a first command from a controller to perform an operation. The method also includes receiving a second command from the controller to perform a read operation, where, the controller does not send a third command to suspend the operation between the first and second commands.

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.