Abstract: A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NMV devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

Abstract: A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.

Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.

Abstract: A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.

Abstract: A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

Abstract: A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.