Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

Abstract: An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

Abstract: A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed.

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.

Abstract: A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

Abstract: An apparatus is described. The apparatus includes a mass storage device having a plurality of storage cells capable of storing more than one bit per cell. The plurality of storage cells are partitionable into a static single level (SLC) buffer, a dynamic SLC buffer and a primary multi-bit storage region. The mass storage device includes charge pump circuitry to program and erase the storage cells such that: a) those of the cells associated with the SLC buffer are to maintain larger stored charge potentials than those of the cells associated with the dynamic SLC buffer; and, b) those of the cells associated with the dynamic SLC buffer, when in SLC mode, are to receive fewer charge pump cycles during a program and/or erase sequence than those of the cells associated with the primary multi-bit storage region.