Patents by Inventor Alice Wang

Alice Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9292025
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 22, 2016
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Patent number: 9285811
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 15, 2016
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Patent number: 9285810
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 15, 2016
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Publication number: 20150022260
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Publication number: 20150025829
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Publication number: 20150022254
    Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Uming Ko, Gordon Gammie, Alice Wang
  • Publication number: 20140315844
    Abstract: Exemplary embodiments of the invention provide methods and compositions relating to a multi-gene signature, and subsets thereof, for predicting whether an individual with breast cancer will respond to chemotherapy based on expression of the genes in the multi-gene signature, as well as for prognosing risk of breast cancer metastasis.
    Type: Application
    Filed: November 27, 2013
    Publication date: October 23, 2014
    Applicant: Celera Corporation
    Inventors: Shirley KWOK, Alice WANG
  • Publication number: 20140179548
    Abstract: The present invention is based on the discovery of a unique 14-gene molecular prognostic signature that is useful for predicting breast cancer metastasis. In particular, the present invention relates to methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information in predicting risk of breast cancer metastasis.
    Type: Application
    Filed: November 19, 2013
    Publication date: June 26, 2014
    Applicant: CELERA CORPORATION
    Inventors: Kit LAU, Alice WANG
  • Publication number: 20140095919
    Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.
    Type: Application
    Filed: September 25, 2013
    Publication date: April 3, 2014
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Hugh Thomas Mair, Gordon Gammie, Alice Wang, Uming Ko
  • Patent number: 8614058
    Abstract: The present invention is based on the discovery of a unique 14-gene molecular prognostic signature that is useful for predicting breast cancer metastasis. In particular, the present invention relates to methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information in predicting risk of breast cancer metastasis.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 24, 2013
    Assignee: Celera Corporation
    Inventors: Kit Lau, Alice Wang
  • Patent number: 8572541
    Abstract: A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.
    Type: Grant
    Filed: September 5, 2010
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Kumar Singh, Rajarshee P. Bharadwaj, Rolf Lagerquist, Alice Wang
  • Patent number: 8557525
    Abstract: The present invention relates to a composite metastasis score (“cMS”) based on expression of a 14-gene molecular signature (referred to as a metastasis score, or “MS”) in combination with progesterone receptor (PR) expression that is useful for predicting breast cancer metastasis. In preferred embodiments, the cMS is determined by applying weighted coefficients to MS and PR. The present invention provides methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information for predicting risk of breast cancer metastasis, among other embodiments.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 15, 2013
    Assignee: Celera Corporation
    Inventors: Alice Wang, Robert J. Lagier, Charles M. Rowland
  • Publication number: 20130222069
    Abstract: Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Arun Paidimarri, Danielle Griffith, Alice Wang
  • Patent number: 8302047
    Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 30, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Dennis Darcy Buss, Alice Wang, Gordon Gammie, Jle Gu, Rahul Jagdish Rithe, Satyendra R. P. Raju Datla, Sharon Hsiao-Wei Chou
  • Publication number: 20120060138
    Abstract: A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.
    Type: Application
    Filed: September 5, 2010
    Publication date: March 8, 2012
    Inventors: Nitin Kumar Singh, Rajarshee P. Bharadwaj, Rolf Lagerquist, Alice Wang
  • Patent number: 8051313
    Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
  • Publication number: 20110216619
    Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
    Type: Application
    Filed: May 12, 2011
    Publication date: September 8, 2011
    Inventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
  • Patent number: 7961546
    Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
  • Patent number: 7920020
    Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 5, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Alice Wang, Hugh T. Mair, Gordon Gammie, Uming Ko
  • Publication number: 20100323921
    Abstract: The present invention is based on the discovery of a unique 14-gene molecular prognostic signature that is useful for predicting breast cancer metastasis. In particular, the present invention relates to methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information in predicting risk of breast cancer metastasis.
    Type: Application
    Filed: December 15, 2009
    Publication date: December 23, 2010
    Applicant: CELERA CORPORATION
    Inventors: Kit LAU, Alice WANG