Patents by Inventor Alice Wang
Alice Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100287517Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.Type: ApplicationFiled: April 23, 2010Publication date: November 11, 2010Inventors: Dennis Darcy Buss, Alice Wang, Gordon Gammie, Jie Gu, Rahul Jagdish Rithe, Satyendra R.P. Raju Datla, Sharon Hsiao-Wei Chou
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Publication number: 20100253387Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.Type: ApplicationFiled: June 11, 2010Publication date: October 7, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: ALICE WANG, HUGH T. MAIR, GORDON GAMMIE, UMING KO
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Patent number: 7793119Abstract: One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.Type: GrantFiled: December 21, 2006Date of Patent: September 7, 2010Assignee: Texas Instruments IncorporatedInventors: Gordon Gammie, Alice Wang, Hugh Thomas Mair
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Patent number: 7760011Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.Type: GrantFiled: November 29, 2007Date of Patent: July 20, 2010Assignee: Texas Instruments IncorporatedInventors: Alice Wang, Hugh T. Mair, Gordon Gammie, Uming Ko
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Publication number: 20100103760Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.Type: ApplicationFiled: October 27, 2008Publication date: April 29, 2010Inventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
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Patent number: 7695915Abstract: The present invention is based on the discovery of a unique 14-gene molecular prognostic signature that is useful for predicting breast cancer metastasis. In particular, the present invention relates to methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information in predicting risk of breast cancer metastasis.Type: GrantFiled: January 31, 2008Date of Patent: April 13, 2010Assignee: Celera CorporationInventors: Kit Lau, Alice Wang
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Patent number: 7622955Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.Type: GrantFiled: April 17, 2008Date of Patent: November 24, 2009Assignee: Texas Instruments IncorporatedInventors: Ramaprasath Vilangudipitchai, Sumanth Katte Gururajarao, Hugh T. Mair, Alice Wang, Uming U. Ko, Sushma Honnavara-Prasad
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Publication number: 20090267638Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Applicant: Texas Instruments IncorporatedInventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
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Publication number: 20090262588Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Inventors: RAMAPRASATH VILANGUDIPITCHAI, Sumanth Katte Gururajarao, Hugh T. Mair, Alice Wang, Uming U. Ko, Sushma Honnavara-Prasad
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Patent number: 7498870Abstract: A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.Type: GrantFiled: January 28, 2005Date of Patent: March 3, 2009Assignee: Texas Instruments IncorporatedInventors: Hugh T. Mair, Gordon Gammie, Alice Wang
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Publication number: 20090046519Abstract: A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing.Type: ApplicationFiled: August 15, 2007Publication date: February 19, 2009Applicant: Texas Instruments IncorporatedInventors: Alice Wang, David Scott, Sumanth Gururajarao, Gordon Gammie, Sudha Thiruvengadam
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Publication number: 20090039952Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.Type: ApplicationFiled: November 29, 2007Publication date: February 12, 2009Inventors: Alice Wang, Hugh T. Mair, Gordon Gammie, Uming Ko
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Publication number: 20080307240Abstract: An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Franck Dahan, Gilles Dubost, Gordon Gammie, Uming Ko, Hugh Mair, Sang-Won Song, Alice Wang, William D. Wilson
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Publication number: 20080206769Abstract: The present invention is based on the discovery of a unique 14-gene molecular prognostic signature that is useful for predicting breast cancer metastasis. In particular, the present invention relates to methods and reagents for detecting and profiling the expression levels of these genes, and methods of using the expression level information in predicting risk of breast cancer metastasis.Type: ApplicationFiled: January 31, 2008Publication date: August 28, 2008Applicant: APPLERA CORPORATIONInventors: Kit Lau, Alice Wang
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Publication number: 20080155282Abstract: One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Gordon Gammie, Alice Wang, Hugh Thomas Mair
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Patent number: 7376038Abstract: A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.Type: GrantFiled: March 21, 2006Date of Patent: May 20, 2008Assignee: Texas Instruments IncorporatedInventors: Sudha Thiruvengadam, Ramaprasath Vilangudipitchai, David B. Scott, Uming U. Ko, Alice Wang
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Patent number: 7307471Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.Type: GrantFiled: August 26, 2005Date of Patent: December 11, 2007Assignee: Texas Instruments IncorporatedInventors: Gordon Gammie, Alice Wang, Uming U. Ko, David B. Scott
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Publication number: 20070223294Abstract: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Applicant: Texas Instruments IncorporatedInventors: Sudha Thiruvengadam, Ramaprasath Vilangudipitchai, David Scott, Uming Ko, Alice Wang
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Publication number: 20070046362Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.Type: ApplicationFiled: August 26, 2005Publication date: March 1, 2007Applicant: Texas Instruments IncorporatedInventors: Gordon Gammie, Alice Wang, Uming Ko, David Scott
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Publication number: 20060175606Abstract: A system and method for enabling a device to function at a subthreshold voltage level of the device is provided. Generally, the system contains a subthreshold data memory capable of functioning when a supply voltage is within the subthreshold voltage level of the device. The system also contains control logic and a read only memory capable of functioning when the supply voltage is within the subthreshold voltage level of the device.Type: ApplicationFiled: February 4, 2005Publication date: August 10, 2006Inventors: Alice Wang, Anantha Chandrakasan