Abstract: A multi layered copper bond pad for a semiconductor die which inhibits formation of copper oxide is disclosed. A small dose of titanium is implanted in the copper surface. The implanted titanium layer suppresses the copper oxide growth in the copper bond pad by controlling the concentration of vacancies available to the copper ion transport. An interconnect structure such as a wire bond or a solder ball may be attached to the copper-boron layer to connect the semiconductor die to a lead frame or circuit support structure. In another embodiment, a titanium-aluminum passivation layer for copper surfaces is also disclosed. The titanium-aluminum layer is annealed to form a titanium-aluminum-copper alloy. The anneal may be done in a nitrogen environment to form a titanium-aluminum-copper-nitrogen alloy.

Abstract: A method of fabricating a contact for electrical connection to a conductive element of an integrated circuit includes partially forming a via in a layer over the conductive element. The via can be defined by an opening in a photoresist pattern. The photoresist pattern is removed prior to exposure of the conductive element at a bottom of the via, and a blanket etch is subsequently performed to expose the conductive element at the bottom of the via. Removing the photoresist pattern can include stripping the photoresist pattern in an ambient comprising oxygen. The via then can be substantially filled with a conductive material. The techniques are particularly advantageous when the previously-formed conductive element is easily oxidizable, for example, where the conductive element includes copper. The techniques can obviate the need to employ less desirable organic solvents to remove the photoresist masks and can improve the quality of the electrical contact.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: A multi layered copper bond pad for a semiconductor die which inhibits formation of copper oxide is disclosed. A small dose of titanium is implanted in the copper surface. The implanted titanium layer suppresses the copper oxide growth in the copper bond pad by controlling the concentration of vacancies available to the copper ion transport. An interconnect structure such as a wire bond or a solder ball may be attached to the copper-boron layer to connect the semiconductor die to a lead frame or circuit support structure. In another embodiment, a titanium-aluminum passivation layer for copper surfaces is also disclosed. The titanium-aluminum layer is annealed to form a titanium-aluminum-copper alloy. The anneal may be done in a nitrogen environment to form a titanium-aluminum-copper-nitrogen alloy.

Abstract: A multilayer structure is provided which suppresses hillock formation due to post-heat treatment steps in thin aluminum films deposited on other substrates by sandwiching the aluminum film between thin layers of aluminum titanium nitride. The first aluminum titanium nitride layer acts as a compatibilizing layer to provide a better match between the coefficients of thermal expansion of the substrate and aluminum metal layer. The second aluminum titanium nitride layer acts as a cap layer to suppress hillock formation.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: In one aspect, the invention includes a semiconductor processing method of reducing corrosion of a material, comprising exposing the material to a liquid solution comprising at least about 5% (by atomic percent) of an oxygen-comprising oxidant to form an oxide layer over the material. In another aspect, the invention includes a semiconductor processing method of forming an aluminum-comprising line within a layer of material, comprising: a) forming a layer of material over a semiconductive substrate; b) forming trenches within the layer of material; c) forming an aluminum-comprising layer within the trenches and over the layer of material; d) planarizing the aluminum-comprising layer to form aluminum-comprising lines within the material, the planarizing comprising abrading a portion of the aluminum-comprising layer with a first fluid, the first fluid comprising a slurry; and e) displacing the slurry with a second fluid comprising at least about 5% (by atomic percent) of ozone.

Abstract: A method of fabricating a contact for electrical connection to a conductive element of an integrated circuit includes partially forming a via in a layer over the conductive element. The via can be defined by an opening in a photoresist pattern. The photoresist pattern is removed prior to exposure of the conductive element at a bottom of the via, and a blanket etch is subsequently performed to expose the conductive element at the bottom of the via. Removing the photoresist pattern can include stripping the photoresist pattern in an ambient comprising oxygen. The via then can be substantially filled with a conductive material. The techniques are particularly advantageous when the previously-formed conductive element is easily oxidizable, for example, where the conductive element includes copper. The techniques can obviate the need to employ less desirable organic solvents to remove the photoresist masks and can improve the quality of the electrical contact.

Abstract: Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal interconnect stacks. The steps of the method comprise first providing a silicon substrate, which typically comprises an in-process integrated circuit wafer. Next, an insulating passivation layer is provided on the silicon substrate. The next step is the sputtering of a titanium layer of a given thickness over the passivation. Subsequently, an aluminum film of three times the thickness of the titanium layer is sputtered over the titanium layer. The next step comprises annealing the titanium layer and the aluminum film in situ in a metal anneal chamber to form titanium aluminide. Following the in situ anneal, the remainder of the needed aluminum is sputtered over the titanium aluminide and a further passivation layer of titanium nitride is then sputtered over the aluminum.

Abstract: A method for forming Dual Damascene structures wherein a via is etched to an element to be contacted, a non-photoreactive protective layer is deposited in the via, and an intersecting trench is formed. The protective layer is then removed, together with any residual debris resulting from the trench formation. The protective layer enhances reliability of the electrical contact at the bottom of the via.

Abstract: Improved methods for filling openings in silicon substrates with copper and the metal interconnects so produced are provided. One method involves the use of a TixAlyNz barrier layer which is stable to the high temperatures required to reflow copper after PVD deposition. Another method involves the use of an aluminum wetting layer between a barrier layer and the copper which effectively lowers the temperature at which copper reflows and therefore allows the use of typical barrier layers.

Abstract: The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and/or refractory metal nitride liners that assist in filling of the contacts. Additionally disclosed is the combination of shallow junction fabrication and high aspect-ratio contact formation to form contacts between a shallow junction and microcircuitry wiring. More particularly, the present invention relates to aluminum filled contacts that fill contact corridors, trenches, or vias in semiconductor devices that are initially lined with a titanium layer and at least one other layer. Preferred other layers include CVD, PVD, or reacted TiN, Co, Ge, and Si.

Abstract: A multilayer structure is provided which suppresses hillock formation due to post-heat treatment steps in thin aluminum films deposited on other substrates by sandwiching the aluminum film between thin layers of aluminum titanium nitride. The first aluminum titanium nitride layer acts as a compatibilizing layer to provide a better match between the coefficients of thermal expansion of the substrate and aluminum metal layer. The second aluminum titanium nitride layer acts as a cap layer to suppress hillock formation.

Abstract: In one aspect, the invention includes a semiconductor processing method of reducing corrosion of a material, comprising exposing the material to a liquid solution comprising at least about 5% (by atomic percent) of an oxygen-comprising oxidant to form an oxide layer over the material. In another aspect, the invention includes a semiconductor processing method of forming an aluminum-comprising line within a layer of material, comprising: a) forming a layer of material over a semiconductive substrate; b) forming trenches within the layer of material; c) forming an aluminum-comprising layer within the trenches and over the layer of material; d) planarizing the aluminum-comprising layer to form aluminum-comprising lines within the material, the planarizing comprising abrading a portion of the aluminum-comprising layer with a first fluid, the first fluid comprising a slurry; and e) displacing the slurry with a second fluid comprising at least about 5% (by atomic percent) of ozone.

Abstract: The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and/or refractory metal nitride liners that assist in filling of the contacts. Additionally disclosed is the combination of shallow junction fabrication and high aspect-ratio contact formation to form contacts between a shallow junction and microcircuitry wiring. More particularly, the present invention relates to aluminum filled contacts that fill contact corridors, trenches, or vias in semiconductor devices that are initially lined with a titanium layer and at least one other layer. Preferred other layers include CVD, PVD, or reacted TiN, Co, Ge, and Si.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal interconnect stacks. The steps of the method comprise first providing a silicon substrate, which typically comprises an in-process integrated circuit wafer. Next, an insulating passivation layer is provided on the silicon substrate. The next step is the sputtering of a titanium layer of a given thickness over the passivation. Subsequently, an aluminum film of three times the thickness of the titanium layer is sputtered over the titanium layer. The next step comprises annealing the titanium layer and the aluminum film in situ in a metal anneal chamber to form titanium aluminide. Following the in situ anneal, the remainder of the needed aluminum is sputtered over the titanium aluminide and a further passivation layer of titanium nitride is then sputtered over the aluminum.