Abstract: A scalable driving architecture for large size display includes a display; a low voltage integrated circuit configured to: receive a high-speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a first high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provide the uncompressed pixel data to the first high voltage integrated circuit via a first low-to-high (L2H) interface, and wherein the low voltage integrated circuit and the first high voltage integrated circuit are assembled on a film.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A low power architecture for mobile displays includes a display, a low voltage integrated circuit configured to: receive a high speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provides the uncompressed pixel data to the high voltage integrated circuit via a timing-to-driver (T2D) interface.

Abstract: Provided is a method of reducing power consumption by a display device including an encoder for receiving a stream of data, and for compressing the data, a TX rate-buffer for receiving and storing the compressed data, a PHY for receiving the compressed data, a RX rate-buffer for receiving and storing the compressed data, and a decoder for receiving the compressed data, and for decompressing the compressed data to reconstruct original data, the method including placing the PHY a SLEEP state to reduce power consumption of the PHY when the TX rate-buffer transmits a last bit of the compressed data in the TX rate-buffer to the PHY, and placing the PHY in a TRANSMIT/ACTIVE state when a fullness of the TX rate-buffer reaches a reference threshold, or a last bit of compressed data corresponding to a last pixel of a line of pixels is placed in the TX rate-buffer.

Abstract: A system for word alignment. In some embodiments, the system includes a deserializer circuit, an alignment detection circuit, and a clock generator circuit. The clock generator circuit has a plurality of enable outputs connected to a plurality of enable inputs of the deserializer circuit, and a plurality of clock outputs connected to a plurality of clock inputs of the deserializer circuit. The alignment detection circuit is configured to detect a coarse word alignment; and, in response to detecting the coarse word alignment, to cause a reset of the clock generator circuit.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Abstract: A system for word alignment. In some embodiments, the system includes a deserializer circuit, an alignment detection circuit, and a clock generator circuit. The clock generator circuit has a plurality of enable outputs connected to a plurality of enable inputs of the deserializer circuit, and a plurality of clock outputs connected to a plurality of clock inputs of the deserializer circuit. The alignment detection circuit is configured to detect a coarse word alignment; and, in response to detecting the coarse word alignment, to cause a reset of the clock generator circuit.

Abstract: Provided is a method of reducing power consumption by a display device including an encoder for receiving a stream of data, and for compressing the data, a TX rate-buffer for receiving and storing the compressed data, a PHY for receiving the compressed data, a RX rate-buffer for receiving and storing the compressed data, and a decoder for receiving the compressed data, and for decompressing the compressed data to reconstruct original data, the method including placing the PHY a SLEEP state to reduce power consumption of the PHY when the TX rate-buffer transmits a last bit of the compressed data in the TX rate-buffer to the PHY, and placing the PHY in a TRANSMIT/ACTIVE state when a fullness of the TX rate-buffer reaches a reference threshold, or a last bit of compressed data corresponding to a last pixel of a line of pixels is placed in the TX rate-buffer.

Abstract: Provided is a method of reducing power consumption by a display device including a display logic for processing pixel data, and a display panel including a plurality of pixels, the method including receiving the pixel data corresponding to the plurality of pixels, determining whether a number of consecutive pixels of the plurality of pixels that correspond to identical data of the pixel data reaches a threshold number, and powering down the display logic when the number of consecutive pixels exceeds the threshold number.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Abstract: A scalable driving architecture for large size display includes a display; a low voltage integrated circuit configured to: receive a high-speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a first high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provide the uncompressed pixel data to the first high voltage integrated circuit via a first low-to-high (L2H) interface, and wherein the low voltage integrated circuit and the first high voltage integrated circuit are assembled on a film.

Abstract: A low power architecture for mobile displays includes a display, a low voltage integrated circuit configured to: receive a high speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provides the uncompressed pixel data to the high voltage integrated circuit via a timing-to-driver (T2D) interface.

Abstract: A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.