Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Abstract: A low power architecture for mobile displays includes a display, a low voltage integrated circuit configured to: receive a high speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provides the uncompressed pixel data to the high voltage integrated circuit via a timing-to-driver (T2D) interface.

Abstract: A scalable driving architecture for large size display includes a display; a low voltage integrated circuit configured to: receive a high-speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a first high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provide the uncompressed pixel data to the first high voltage integrated circuit via a first low-to-high (L2H) interface, and wherein the low voltage integrated circuit and the first high voltage integrated circuit are assembled on a film.

Abstract: A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.

Abstract: A display device comprises a display panel having a plurality of pixels arranged in pixel rows and pixel columns, and a source circuit. The source circuit includes a plurality of signal lines, each signal line coupled to each pixel of a pixel column; a plurality of column drivers, each column driver connected to one of the signal lines so as to transmit pixel voltages to the pixels of its respective pixel column, the pixel voltages corresponding to image data values for displaying an image upon the display panel; and a plurality of pixel refresh circuits. Each pixel refresh circuit corresponds to one of the signal lines and is coupled to the respective column driver so as to be arranged to determine a voltage stored in the corresponding pixel and to transmit a refresh signal to the respective column driver to refresh the voltage stored in the corresponding pixel.

Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.

Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.