Abstract: A chain of bidirectional display driver integrated circuits (DICs). The chain has a beginning and an end, the chain includes a plurality of DICs, each of the plurality of DICs including: a direct data input, a relay data input, and a relay data output. Each of the plurality of DICs is configured to combine data received at the direct data input with a stream of bits received at the relay data input to form combined data, and to transmit the combined data through the relay data output.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

Abstract: A method of calibrating coefficients of a calibrated decision feedback equalizer (DFE) across a process, voltage, and temperature (PVT) range, the calibrated DFE comprising a plurality of DFE taps for reducing distortions of an input signal, and a sampler for sampling the input signal, the method including applying a preset voltage to an input of the calibrated DFE, setting a DFE tap of the plurality of DFE taps to a maximum value, generating a source reference, via a source reference calibrator, to apply to the DFE tap, changing the source reference to a first level that causes an output of the sampler to transition from a first state to a second state, determining the first level as a calibrated source reference, and applying the calibrated source reference to the DFE tap during normal operation of the calibrated DFE.

Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

Abstract: According to some embodiments of the present invention, a display device includes: a display panel; and an integrated circuit (IC) assembly coupled to the display panel, the IC assembly comprising: a flexible substrate; a first flexible thermally conductive layer on the flexible substrate; and an IC chip on the flexible substrate and thermally coupled to the first flexible thermally conductive layer.

Abstract: A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.

Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.

Abstract: A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.

Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A receiver for a serial link. The receiver has an analog input configured to receive a received signal and includes a first front end comprising a first sampler configured to sample a signal at an input of the first front end, and a first correction circuit configured to add a first correction to the signal at the input of the first front end, the first correction including a first offset correction. The offset correction is updated by a modified sign-sign least mean squares method.

Abstract: A system for starting a point-to-multi-point serial communications system. The system includes a transmitter having a sync connection and a plurality of data outputs and a plurality of receivers, each of the plurality of receiver having a sync connection and a data input; the data input of each of the plurality of receivers being connected to a respective one of the plurality of data outputs of the transmitter; and the sync connection of the transmitter being connected, by a conductor, to the sync connection of each of the plurality of receivers, each of the plurality of receivers comprising a first impedance and a first switch, the first impedance and the first switch configured to establish, when the first switch is closed, a current path between the sync connection of the receiver and a first voltage source in the receiver.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A system for transmitting data from a timing controller (TCON) to several source driver integrated circuits (SICs) in a display. The system is suitable for use either with a high data rate or a low data rate to each of the SICs. The TCON provides a serial data stream to a SIC, which either uses all of the received data, if it requires high rate data, or relays a portion, e.g., half, of the data to another SIC, which then does not require a separate direct connection to the TCON.