Patents by Inventor Amit Verma

Amit Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200195707
    Abstract: Method for transferring data from a device to a data management means, switching unit, device and system The invention relates to a method for transferring data (16) from a device (6) to a data management means (4). In order to reduce the amount of data transferred and according to the method of the invention, using modeling data (26, 42) present in the device (6) a model (30, 44) described by the modeling data (26, 42) is determined. Using the model (30, 44), the data that is actually to be transferred to the data management means (4) is selected from a volume of data (40) provided for transfer. The device (6) transfers the selected data to the data management means (4).
    Type: Application
    Filed: April 13, 2018
    Publication date: June 18, 2020
    Inventor: Amit Verma
  • Patent number: 10637447
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 28, 2020
    Inventors: Alok Kumar Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal
  • Patent number: 10616083
    Abstract: A device network communicates with a remote platform such as a cloud service via a gateway. A network monitor device monitors network health and may adjust the amount of data collected by the gateway, reducing the amount of data collected in case of poor network health.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 7, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Amit Verma
  • Patent number: 10546083
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Verma, Suyash Kumar, Habeeb Farah
  • Patent number: 10515169
    Abstract: The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating the formal data set using a user-programmable consolidation function to generate a combined formal coverage data set.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Ryan Spatafore, Amit Verma, Anubhav Srivastava
  • Publication number: 20190379706
    Abstract: A method is provided for securely connecting devices to the cloud by virtue of a particular device being connected to a concierge service of the cloud and transmitting information relating to the security functions offered by the device to the service, whereupon the concierge service determines, based on the information which is transmitted by the requesting device and relates to the security functions of the latter, a security profile which is appropriate for the device and connects the requesting device to a communication channel appropriate for the determined security profile.
    Type: Application
    Filed: October 18, 2017
    Publication date: December 12, 2019
    Inventor: Amit Verma
  • Patent number: 10475942
    Abstract: A photodetector cell may include a substrate, and a first contact carried by the substrate and having a first work function value. The photodetector cell may include a second contact carried by the substrate and having a second work function value different from the first work function value, and a semiconductor wire carried by the substrate and having a third work function value between the first and second work function values. The semiconductor wire may be coupled between the first and second contacts and comprising a photodiode junction.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 12, 2019
    Inventors: Manjeri P. Anantram, Md Golam Rabbani, Mahmoud M. Khader, Reza Nekovei, Amit Verma
  • Publication number: 20190273484
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 5, 2019
    Inventors: Alok Kumar TRIPATHI, Amit VERMA, Anuj GROVER, Deepak Kumar BIHANI, Tanmoy ROY, Tanuj AGRAWAL
  • Patent number: 10353348
    Abstract: A system executing a closed loop control on data for cloud-based applications includes an industrial automation device configured to generate cloud variables, a cloud-based application on a network device with cloud-computing infrastructure, an industrial controller controlling the industrial automation device by a user-defined program which receives the cloud variables, a cloud agent communicating with the user-defined control program and the cloud-based application. The cloud agent collects the cloud variables and sends them to the cloud-based application. The cloud-based application determines updated optimized cloud variables and notifies the cloud agent with the updated optimized cloud variables. The cloud agent reloads the updated optimized cloud variables and notifies the user-defined control program with the updated optimized cloud variables.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 16, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Amit Verma
  • Patent number: 10303128
    Abstract: In a system and a method for control and/or analytics of an industrial process and especially a system and a method for the prioritization of the data transmission of process data from plant-side automation and processing units to remote processing units external to the plant, the system has an the plant side at least one automation or processing unit, which carries out first process variable computations and acts on the process. On the side external to the plant, the system has a remote processing unit that carries out a number of second process variable computations and that receives local data from the at least one automation or processor unit via a data connection and at least one data collector unit. The data collector unit prioritizes the data transfer via the data connection between the at least one automation or processor unit and the processing unit external to the plant.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 28, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventor: Amit Verma
  • Patent number: 10277207
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 30, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Alok Kumar Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal
  • Publication number: 20190058644
    Abstract: A device network communicates with a remote platform such as a cloud service via a gateway. A network monitor device monitors network health and may adjust the amount of data collected by the gateway, reducing the amount of data collected in case of poor network health.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Inventor: Amit Verma
  • Patent number: D843246
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Johnson Controls Technology Company
    Inventors: Sudhi Sinha, Joseph R. Ribbich, Michael L. Ribbich, Charles J. Gaidish, John Peter Cipolla, Amit Verma, Vinosh C. Diptee, Hao A. Nguyen, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Patricia Ellis Douglass, Claudio Santiago Ribeiro
  • Patent number: D843247
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 19, 2019
    Assignee: Johnson Controls Technology Company
    Inventors: Joseph R. Ribbich, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D849569
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 28, 2019
    Assignee: JOHNSON CONTROLS TECHNOLOGY COMPANY
    Inventors: Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D852067
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 25, 2019
    Assignee: Johnson Controls Technology Company
    Inventors: Joseph R. Ribbich, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D876260
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 25, 2020
    Assignee: Johnson Controls Technology Company
    Inventors: Joseph R. Ribbich, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D876971
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: March 3, 2020
    Assignee: Johnson Controls Technology Company
    Inventors: Joseph R. Ribbich, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D884526
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 19, 2020
    Assignee: Johnson Controls Technology Company
    Inventors: Joseph R. Ribbich, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Vinosh C. Diptee, Patricia Ellis Douglass, Hao A. Nguyen, Claudio Santiago Ribeiro, Amit Verma
  • Patent number: D885942
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 2, 2020
    Assignee: Johnson Controls Technology Company
    Inventors: Sudhi Sinha, Joseph R. Ribbich, Michael L. Ribbich, Charles J. Gaidish, John Peter Cipolla, Amit Verma, Vinosh C. Diptee, Hao A. Nguyen, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Patricia Ellis Douglass, Claudio Santiago Ribeiro