Patents by Inventor Ammar Derraa

Ammar Derraa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6552478
    Abstract: Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. In a field emission array, a conductive element may contact each resistor of a line of pixels. A method for fabricating the field emission array includes forming a plurality of substantially parallel conductive lines, depositing at least one layer of semiconductive or conductive material over and laterally adjacent each conductive line, and forming a hard mask in recesses of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tips and resistors. At least the substantially central longitudinal portions of the conductive traces are removed to form the conductive elements.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 22, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6548947
    Abstract: A method for fabricating row lines over a field emission array in which two mask steps are used to define row lines and pixel openings through selected regions of each row line. A first mask may be employed in the removal of dielectric material and conductive material from between pixel rows and from substantially above each pixel of the field emission array. A second mask may be used in the removal of semiconductor material from between the adjacent rows of pixels. Alternatively, a first mask may be employed in the definition of row lines, while a second mask may be used in the formation of pixel openings. Field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines are also disclosed.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 15, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Publication number: 20030048071
    Abstract: A field emission array includes a dielectric structure with at least two dielectric layers between the cathode and anode grid thereof. The lower dielectric layer is planarized to minimize the occurrence of electrical shorts between the cathode and anode grid of the field emission array. Thus, the upper dielectric layer is substantially free of any electrically conductive defects or imperfections that extend through the lower dielectric layer. In addition, the field emission array includes an array of emitter tips, which are laterally surrounded and may be spaced apart from the dielectric structure. The field emission array may also include a grid over the dielectric structure and the emitter tips, with the emitter tips being exposed through grid openings or apertures.
    Type: Application
    Filed: October 7, 2002
    Publication date: March 13, 2003
    Inventor: Ammar Derraa
  • Publication number: 20030042606
    Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventor: Ammar Derraa
  • Publication number: 20030042607
    Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: Ammar Derraa, Sujit Sharan, Paul Castrovillo
  • Publication number: 20030042550
    Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Ammar Derraa, Sujit Sharan, Paul Castrovillo
  • Publication number: 20030025206
    Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventors: Ammar Derraa, Sujit Sharan, Paul Castrovillo
  • Publication number: 20030001489
    Abstract: Field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies are described. In one embodiment, a substrate is provided having a column line formed and supported thereby. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. At least some of the regions define different pixels of the display. A continuous resistor is interposed between the column line and at least two different pixels. In another embodiment, a column line is formed and supported by a substrate. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. The regions define different pixels of the display. A single current-limiting resistor is operably coupled with the column line and at least two different pixels. In yet another embodiment, a series of column lines are formed over a substrate.
    Type: Application
    Filed: March 1, 1999
    Publication date: January 2, 2003
    Inventor: AMMAR DERRAA
  • Patent number: 6498425
    Abstract: A field emission array includes a dielectric structure with at least two dielectric layers between the cathode and anode grid thereof. The lower dielectric layer is planarized to minimize the occurrence of electrical shorts between the cathode and anode grid of the field emission array. Thus, the upper dielectric layer is substantially free of any electrically conductive defects or imperfections that extend through the lower dielectric layer. In addition, the field emission array includes an array of emitter tips, which are laterally surrounded and may be spaced apart from the dielectric structure. The field emission array may also include a grid over the dielectric structure and the emitter tips, with the emitter tips being exposed through grid openings or apertures.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: December 24, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Publication number: 20020163294
    Abstract: Methods of forming base plates for field emission display (FED) devices, methods of forming field emission display (FED) devices, and resultant FED base plate and device constructions are described. In one embodiment, a substrate is provided and is configurable into a base plate for a field emission display. A plurality of discrete, segmented regions of field emitter tips are formed by at least removing portions of the substrate. The regions are electrically isolated into separately-addressable regions. In another embodiment, a plurality of field emitters are formed from material of the substrate and arranged into more than one demarcated, independently-addressable region of emitters. Address circuitry is provided and is operably coupled with the field emitters and configured to independently address individual regions of the emitters.
    Type: Application
    Filed: February 17, 1999
    Publication date: November 7, 2002
    Inventor: AMMAR DERRAA
  • Patent number: 6461211
    Abstract: In one aspect, an electron emission device comprises a substrate, and a first layer supported by the substrate. The first layer comprises a conductive material. The electron emission display device further comprises an electron emission tip electrically connected with the first layer, and a second layer electrically disposed between the first layer and the electron emission tip. The second layer comprises microcrystalline silicon. In another aspect, the invention encompasses a method of forming an electron emission device. A substrate is provided, and a conductive layer is formed over the substrate. A microcrystalline-silicon-containing layer is formed over the conductive layer, and a resistor layer is formed over the microcrystalline-silicon-containing layer. An emitter tip is formed over the resistor layer. In yet other aspects, the invention encompasses field emission display devices, and methods of forming field emission display devices.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kanwal K. Raina, Ammar Derraa
  • Publication number: 20020142499
    Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.
    Type: Application
    Filed: May 29, 2002
    Publication date: October 3, 2002
    Inventor: Ammar Derraa
  • Publication number: 20020137241
    Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.
    Type: Application
    Filed: May 13, 2002
    Publication date: September 26, 2002
    Inventor: Ammar Derraa
  • Publication number: 20020121850
    Abstract: A method of fabricating row lines and pixel openings of a field emission array. The method employs only two masks. A first mask employed in the method includes apertures alignable between rows of pixels of the field emission array. Electrically conductive material and semiconductive material exposed through the apertures are removed to define the row lines of the field emission array. A passivation layer is then disposed over at least selected portions of the field emission array. Then a second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer of the field emission array. Passivation material exposed through the apertures of the second mask is removed to define openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may then be removed to expose the underlying semiconductive grid and to further define the pixel openings.
    Type: Application
    Filed: March 28, 2002
    Publication date: September 5, 2002
    Inventor: Ammar Derraa
  • Patent number: 6443788
    Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Publication number: 20020113536
    Abstract: Field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies are described. In one embodiment, a substrate is provided having a column line formed and supported thereby. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. At least some of the regions define different pixels of the display. A continuous resistor is interposed between the column line and at least two different pixels. In another embodiment, a column line is formed and supported by a substrate. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. The regions define different pixels of the display. A single current-limiting resistor is operably coupled with the column line and at least two different pixels. In yet another embodiment, a series of column lines are formed over a substrate.
    Type: Application
    Filed: April 1, 2002
    Publication date: August 22, 2002
    Inventor: Ammar Derraa
  • Publication number: 20020102900
    Abstract: An emission structure includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. The conductive element may contact the resistor. A method for fabricating the emission structure includes forming at least one conductive line, depositing at least one layer of semiconductive or conductive material over and laterally adjacent the at least one conductive line, and forming a hard mask in recessed areas of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tip and resistor. At least the substantially central longitudinal portion of the conductive trace is removed to form the conductive element.
    Type: Application
    Filed: April 2, 2002
    Publication date: August 1, 2002
    Inventor: Ammar Derraa
  • Publication number: 20020102759
    Abstract: A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantially removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.
    Type: Application
    Filed: April 2, 2002
    Publication date: August 1, 2002
    Inventor: Ammar Derraa
  • Patent number: 6417627
    Abstract: A matrix-addressable device includes a number of metal column lines having a number of windows underlying locations of intersection where a number of metal row lines overlap or cross the column lines. Each of the windows has a length that is greater than the nominal width of the row line crossing the column line. A layer of a doped semiconductor overlaps each of the windows to electrically couple a number of emitters formed on the doped semiconductor to the column lines. Each of the metal row lines may include a number of windows positioned at the locations where the row and column lines overlap. Each of the windows has a length greater than a nominal width of the column line that the window overlays. A doped semiconductor layer covers each of the windows and is electrically coupled thereto. A number of apertures formed in the doped semiconductor layer aligned with the emitters to form an extraction grid. A layer of dielectric material may separate the column lines from the row lines.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: July 9, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6406927
    Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 18, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa