Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.

Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

Abstract: Disclosed is a small-size vertical-type light emitting diode chip with high luminous in a central region. A PN junction structure is arranged on a light emitting region base of an interface structure, the interface structure is provided with a P-type Ohmic contact area at the light emitting region base, a central area of the PN junction structure is above the P-type Ohmic contact area, an insulating layer is formed on an extending platform adjacent to the light emitting region base and extends to cover an N-type semiconductor of the PN junction structure to form a border covering region surrounding the N-type semiconductor, an N-type Ohmic contact electrode covers the border covering region, and an N-type electrode pad is arranged on the insulating layer and electrically connected with the N-type Ohmic contact electrode via a bridging connected metal layer.

Abstract: The invention is a small-sized vertical light emitting diode chip with high energy efficiency, wherein a PN junction structure is arranged on a light-emitting region platform of an interface structure; a highly reflective metal layer is arranged under the light-emitting region platform; the interface structure is provided with a P-type ohmic contact area under an outwardly extending platform adjacent to the light-emitting region platform; an insulating layer is formed on the outwardly extending platform; an N-type ohmic contact electrode is in ohmic contact with the PN junction structure and covers the border covering region at a position opposite to the outwardly extending platform; the current conduction is achieved diagonally on the opposite sides by locally diagonally symmetric geometric positioning of the N-type ohmic contact electrode and the P-type ohmic contact area.

Abstract: The invention relates to a vertical light-emitting diode chip structure capable of measuring temperature and a temperature measurement calibration method thereof. A semiconductor epitaxial structure and a metal film resistance temperature measurement structure are separately arranged on the upper plane of a transverse high thermal conductivity extension structure. Through the high thermal conductivity characteristic of the transverse high thermal conductivity extension structure, the temperature of an active layer of the semiconductor epitaxial structure can be quickly transferred to the metal film resistance temperature measurement structure. The temperature measurement calibration method comprises: placing a plurality of connected and uncut package support plates into a constant temperature device at the same time to obtain a temperature calibration relation for different package support plates at the same time to reduce the temperature calibration cost in a batch mass production mode.

Abstract: The present disclosure provides an overlay mark, an overlay error measurement method for a wafer, and a wafer stacking method. The overlay mark includes a first overlay mark disposed on a first layer, and a second overlay mark disposed on a second layer. The first layer and the second layer are stacked. The first overlay mark includes at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape. The second overlay mark includes a second overlay sub-mark, and the second overlay sub-mark is in a center-symmetrical shape including a plurality of linear graphics.

Abstract: The invention provides an automotive lighting unit for detecting electrical characteristics of light emitter diode component. At least one light emitter diode light source is selectively disposed on any one of at least one circuit channel of at least one drive power loop. At least one circuit breaker comprises at least one circuit switch corresponding to the at least one drive power loop, and is disposed on the circuit channel with the at least one light emitter diode light source. The at least one circuit channel is controlled by the at least one circuit switch to turn in a state of isolating from a drive power. An ammeter connection line is connected with the two sides one of the at least one light emitter diode light source.

Abstract: A method for stacking multi-layer wafers, and a system for stacking multi-layer wafers. The method includes bonding a wafer to a carrier wafer; a first feature pattern being defined in the wafer; acquiring overlay deviation values of different positions of the first feature pattern relative to the carrier wafer; fitting the overlay deviation values corresponding to the different positions and obtaining an actual deviation value of the wafer; and compensating an exposure process of the wafer based on the actual deviation value. In this way, an occurrence of the wafer failing to be exposed and being scrapped due to an alignment accuracy between the wafer and the carrier wafer being lower may be reduced.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: The invention provides a light-emitting diode grain structure with multiple contact points, including a P-type electrode, a conductive base plate, a light-emitting semiconductor layer, a plurality of ohmic contact metal points, a mesh-structured connection conductive layer, a connection point conductive layer, and an N-type electrode pad electrically connected to the connection point conductive layer. The plurality of ohmic contact metal points is arranged on an N-type semiconductor layer in a spreading manner, and is contacted with the N-type semiconductor layer. No ohmic contact is formed between the connection conductive layer and the N-type semiconductor layer. Accordingly, the metal points and the connection conductive layer can disperse a current, reduce a shading area, and improve the luminous efficiency and component reliability; and uniform light emission from a surface facilitates the light distribution uniformity of an original light source and exciting light after phosphor is coated.

Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

Abstract: A vertical light emitting diode structure with high current dispersion and high reliability comprises a conductive substrate with a central region and a side region; a light emitting semiconductor layer is disposed on the central region; an ohmic contact metal layer is disposed at a center of the light emitting semiconductor layer; an N-type electrode is disposed at the side region and is connected with the ohmic contact metal layer and the N-type electrode through an N-type electrode bridging structure; a working current is diffused from the center of the light emitting semiconductor layer to have high current dispersion, so that the problem of heat dissipation of local high current caused by the design that the N-type electrode is disposed on the edge can be solved.

Abstract: The invention provides a light-emitting diode grain structure with multiple contact points, including a P-type electrode, a conductive base plate, a light-emitting semiconductor layer, a plurality of ohmic contact metal points, a mesh-structured connection conductive layer, a connection point conductive layer, and an N-type electrode pad electrically connected to the connection point conductive layer. The plurality of ohmic contact metal points is arranged on an N-type semiconductor layer in a spreading manner, and is contacted with the N-type semiconductor layer. No ohmic contact is formed between the connection conductive layer and the N-type semiconductor layer. Accordingly, the metal points and the connection conductive layer can disperse a current, reduce a shading area, and improve the luminous efficiency and component reliability; and uniform light emission from a surface facilitates the light distribution uniformity of an original light source and exciting light after phosphor is coated.

Abstract: A non-common-ground bandpass filter circuit with electrostatic discharge (ESD) protection is disclosed. The non-common-ground bandpass filter circuit with ESD protection includes a non-common-ground plane, a dielectric substrate and a conductor. The conductor is disposed above the non-common-ground plane. The dielectric substrate is disposed between the conductor and the non-common-ground plane. The non-common-ground plane at least has a first ground region and a second ground region separated and insulated from each other. The first ground region corresponds to a first terminal of the conductor and the second ground region corresponds to a second terminal of the conductor. When an ESD event occurs on one of the first ground region and the second ground region, the other of the first ground region and the second ground region will not be damaged by the ESD event. The non-common-ground bandpass filter circuit also provides surge protection.

Abstract: A flip-chip light-emitting diode structure capable of emitting trichromatic spectrum and a manufacturing method thereof, including a blue-green light layer with a light-stimulated green light-emitting structure and an electron-stimulated blue light-emitting structure, a bonding layer and a red light layer with a light-stimulated red light-emitting structure. The manufacturing method uses a sapphire bonding layer as the bonding layer, and forming the blue-green light layer and the red light layer by growing epitaxy on two sides of the sapphire bonding layer; or, after growing the blue-green light layer and the red light layer by epitaxy respectively, uses the bonding layer to connect.

Abstract: A vertical light emitting diode structure with high current dispersion and high reliability comprises a conductive substrate with a central region and a side region; a light emitting semiconductor layer is disposed on the central region; an ohmic contact metal layer is disposed at a center of the light emitting semiconductor layer; an N-type electrode is disposed at the side region and is connected with the ohmic contact metal layer and the N-type electrode through an N-type electrode bridging structure; a working current is diffused from the center of the light emitting semiconductor layer to have high current dispersion, so that the problem of heat dissipation of local high current caused by the design that the N-type electrode is disposed on the edge can be solved.