Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed.

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

Abstract: A method by a rendering device includes receiving a request to render multiple surfaces corresponding to multiple virtual objects to be concurrently displayed on an augmented-reality (AR) headset. The method further includes that the AR headset is connected to the rendering device via a wireless link. In response to a determination that a network quality of the wireless link is below a threshold condition, the method further includes selecting a first subset of the multiple surfaces that are higher priority than a second subset of the plurality of surfaces. The method includes transmitting the first subset of multiple surfaces to the AR headset for display and transmitting the second subset of multiple surfaces to the AR headset for display after transmitting the first subset. This method includes rendering the surfaces in accordance with a set of rendering parameters so as to satisfy one or more network constraints.

Abstract: A mask includes a main body. The main body includes a first outer layer, a second outer layer, a middle layer, and an inner layer which are sequentially stacked in a stacking direction. The first outer layer and the second outer layer are non-woven fabrics. The first outer layer includes a plurality of first pressed portions. The second outer layer disposed with a plurality of second pressed portions.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Abstract: A fluid transfer guiding/controlling device and an application system thereof. The guiding/controlling device is composed of a power transfer/distribution unit and a switch member. The power transfer/distribution unit has a first chamber and a second chamber. At least one bypass flow ways are disposed in the first chamber. Stop sections are disposed in the second chamber. Communication notches are disposed in adjacency to the stop sections in communication with an outer side. The switch member having an internal flow guide passage and a first flow guide window and a second flow guide window is disposed in the first and second chambers. The first flow guide window is switchable between the bypass flow ways. The second flow guide window is moved from the stop section to pass through a corresponding communication notch, whereby part of the fluid in the flow guide passage flows through the communication notch.

Abstract: The present patent specification provides a medical device including an outer tube, an operation portion and a control portion. The operation portion is at least partially located in the outer tube. The control portion has a channel communicating with the outer tube along a first direction; a second end of the control portion is coupled with a first end of the outer tube so that the channel and the outer tube communicate with each other along the first direction. The control portion includes a control module including a suction control unit, a suction, a suction valve actuator and a switching unit. The suction control unit has a stopping unit and is configured to move along a second direction which is different from the first direction. The suction valve actuator is located at a side opposite the suction control unit with the channel therebetween and the suction valve actuator is configured to be activated by the suction control unit.

Abstract: A computing system may access first alpha values associated with first pixels in a first pixel region of an image and determine a bit budget for encoding the first alpha values. The computing system may then select a first alpha-encoding mode for the first alpha values to reflect a determination that the first alpha values are all fully transparent or all fully opaque, and encode the first alpha values by storing the selected first alpha-encoding mode as part of a metadata without using the bit budget to encode the first alpha values individually. The computing system may then update a record of unallocated bits available for allocation based on the bit budget unused in the encoding of the first alpha values, and allocate, based on the record of unallocated bits, bits to encode a set of alpha values different from the first alpha values.

Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photosensors.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Abstract: A power supply with lightning protection includes a surge voltage suppression apparatus, an electromagnetic interference control circuit, a surge current bypass apparatus, an active bridge rectifier circuit, a power factor correction circuit, and a DC-to-DC conversion circuit. The surge voltage suppression apparatus is used to increase a tolerance of a surge voltage for the power supply. The electromagnetic interference control circuit is coupled to the surge voltage suppression apparatus. The surge current bypass apparatus is used to increase a tolerance of a surge current for the power supply. The active bridge rectifier circuit is used to rectify an input voltage. The power factor correction circuit is used to adjust the rectified input voltage to provide an adjusted input voltage on a bulk capacitor. The DC-to-DC conversion circuit is used to convert the adjusted input voltage into a DC output voltage.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: An image sensor includes a substrate and a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first buffer layer over the substrate. The image sensor further includes a shield layer over the first buffer, wherein the first buffer layer and the shield layer define a first recess aligned with the first PD and a second recess aligned with the second PD. The image sensor further includes a flicker reduction layer in the first recess, wherein the second recess is free of the flicker reduction layer.

Abstract: A switchable two-stage coalescence separation system, including a coalescer housing (1), a plurality of two-stage filter elements (2), and a particle detector (5). A lower portion and an upper portion of each of the two-stage filter elements (2) are located in a lower chamber (101) and an upper chamber (102) of the coalescer housing (1), respectively. Two gas inlet branch pipes are communicated with the lower chamber (101) and the upper chamber (102), respectively and are connected to a gas inlet main pipe (8) through a first multi-way valve (6). The particle detector (5) is disposed on the gas inlet main pipe (8). Two outlet branch pipes are communicated with the lower chamber (101) and the upper chamber (102), respectively and are connected to a gas outlet main pipe 13 through a second multi-way valve (7).