Patents by Inventor An-Cheng Chang

An-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10871647
    Abstract: An EUV collector mirror for an extreme ultra violet (EUV) radiation source apparatus includes an EUV collector mirror body on which a reflective layer as a reflective surface is disposed, a trajectory correcting device attached to or embedded in the EUV collector mirror body and a trajectory correcting device to adjust the trajectory of metal from the reflective surface of the EUV collector mirror body to an opposite side of the EUV collector mirror body.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An Liu, Gwan-Sin Chang, Bharath Kumar Pulicherla, Li-Jui Chen, Sheng-Kang Yu, Chung-Cheng Wu, Zhiqiang Wu
  • Patent number: 10872406
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10872773
    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Publication number: 20200393715
    Abstract: Electrical shield line systems are provided for openings in common electrodes near data lines of display and touch screens. Some displays, including touch screens, can include multiple common electrodes (Vcom) that can have openings between individual Vcoms. Some display screens can have an open slit between two adjacent edges of Vcom. Openings in Vcom can allow an electric field to extend from a data line through the Vcom layer. A shield can be disposed over the Vcom opening to help reduce or eliminate an electric field from affecting a pixel material, such as liquid crystal. The shield can be connected to a potential such that electric field is generated substantially between the shield and the data line to reduce or eliminate electric fields reaching the liquid crystal.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Inventors: Zhibing GE, Cheng-Ho YU, Young-Bae PARK, Abbas JAMSHIDI ROUDBARI, Shih-Chang CHANG, Cheng CHEN, Marduke YOUSEFPOR, John Z. ZHONG
  • Publication number: 20200391033
    Abstract: The invention relates to an electrochemical dephosphorylation technique for treating Alzheimer's disease and a use thereof. It comprises a gold electrode provided with a negative potential of ?0.2 V to ?0.6 V on a surface thereof.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: JUNG-CHIH CHEN, I-CHIU LI, KUN-CHE LI, CHING-CHENG CHUANG, MEI-LAN KO, HSIN-YU CHEN, CHIA-HSUAN CHANG, HSIN-YI TSAI, CHIEN-CHIH HSU
  • Publication number: 20200392134
    Abstract: A method for purifying 2-[[2-[[[3-(4-Chlorophenyl)-8-methyl-8-azabicyclo[3.2.1]-oct-2-yl]methyl](2-mercaptoethyl)amino]ethyl]amino]ethanethiol-[1R-(exo-exo)]-hydrochloride is revealed. After medium pressure liquid chromatography and subsequent acid treatment, 2-[[2-[[[3-(4-Chlorophenyl)-8-methyl-8-azabicyclo[3.2.1]-oct-2-yl]methyl](2-mercaptoethyl)amino]ethyl]amino]ethanethiol-[1R-(exo-exo)]-hydrochloride with high purity is obtained. The method for purifying can solve the problem that the product purity is not up to the standard for radiopharmaceuticals.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 17, 2020
    Inventors: SHOW-WEN LIU, CHENG-FANG HSU, WEI-HSI CHEN, YU CHANG
  • Publication number: 20200393745
    Abstract: The invention provides a projection device which includes a rotating module and an imaging module. The rotating module is assembled on a mounting surface and includes a rotating part and an assembling part which are integrally formed. The rotating part is parallel to the mounting surface, and the assembling part is perpendicular to the mounting surface. The imaging module is assembled on the assembling part of the rotating module. When the rotating module rotates by taking an axis perpendicular to the mounting surface as an axial center, the rotating module drives the imaging module to rotate so as to change a projection direction of the imaging module. The projection device of the invention adjusts the projection direction without using a tool.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 17, 2020
    Applicant: Coretronic Corporation
    Inventors: Jen-Yu Shie, Kuang-Hsiang Chang, Heng Li, Pei-Cheng Liao
  • Publication number: 20200395360
    Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Inventors: Che-Cheng CHANG, Chih-Han LIN, Horng-Huei TSENG
  • Publication number: 20200395609
    Abstract: An anode active material of a lithium-ion battery is provided. The active material of the anode of the lithium-ion battery includes silicon, tin and copper-zinc alloy, in which tin is substantially in an elemental state. Moreover, an anode of a lithium-ion battery is provided. The anode of the lithium-ion battery includes the active material as mentioned above.
    Type: Application
    Filed: December 19, 2019
    Publication date: December 17, 2020
    Inventors: Jui-Shen CHANG, Yun-Shan LO, Kuo-Cheng HUANG
  • Patent number: 10868012
    Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10867865
    Abstract: A semiconductor device includes a substrate and a fin protruding from the substrate, the fin having a first fin segment and a second fin segment discontinued from the first fin segment. The semiconductor device further includes an isolation feature disposed between the first and second fin segments and a spacer feature disposed on sidewalls of an upper portion of the isolation feature and surrounding the isolation feature from a top view.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin
  • Patent number: 10866209
    Abstract: A microfluidic system includes a semiconductor substrate having a first surface and an opposite, parallel second surface, a first bioFET sensor and a second bioFET sensor. An isolation layer is disposed on the second surface of the semiconductor substrate and has a first opening over the first bioFET sensor and a second opening over the second bioFET sensor. An interface layer is disposed in at least each of the first opening and the second opening. The system includes a readout circuit having a differential amplifier designed to measure a difference between signals associated with the first bioFET sensor and the second bioFET sensor. The system also includes a microfluidic network designed to deliver fluid to the interface layer disposed in each of the first opening and the second opening.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 15, 2020
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Tung-Tsun Chen, Yu-Jie Huang, Penny Hsiao
  • Patent number: 10866516
    Abstract: A photoresist layer is coated over a wafer. The photoresist layer includes a metal-containing material. An extreme ultraviolet (EUV) lithography process is performed to the photoresist layer to form a patterned photoresist. The wafer is cleaned with a cleaning fluid to remove the metal-containing material. The cleaning fluid includes a solvent having Hansen solubility parameters of delta D in a range between 13 and 25, delta P in a range between 3 and 25, and delta H in a range between 4 and 30. The solvent contains an acid with an acid dissociation constant less than 4 or a base with an acid dissociation constant greater than 9.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
  • Patent number: 10867921
    Abstract: A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 10868002
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10868139
    Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Ming-Ching Chang, Chan-Lon Yang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10868138
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10868187
    Abstract: In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Yung Jung Chang
  • Patent number: 10868189
    Abstract: A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng