Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.

Abstract: A light-emitting diode is provided. The light-emitting diode includes a P-type semiconductor layer, a N-type semiconductor layer, and a light-emitting stack located therebetween. The light-emitting stack includes a plurality of well layers and a plurality of barrier layers that are alternately stacked, the well layers includes at least one first well layer, at least one second well layer, and third well layers that have different indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of well layers that are closest to the P-type semiconductor layer are the third well layers, and the first well layer is closer to the N-type semiconductor layer than the P-type semiconductor layer.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.

Abstract: A method for forming sense amplifiers of a memory device includes: determining a type of each bitline selector used to provide a data signal to a corresponding sense amplifier; forming a plurality of separate active areas in a substrate of the memory device along one of a column direction and a row direction according to the type of the bitline selector, the substrate including a plurality of cell columns, each of the cell columns having a plurality of memory cells arranged along the column direction, each of the active areas being formed across a boundary between two adjacent cell columns and located within the adjacent cell columns; and arranging a plurality of gate structures on the active areas to form transistors of the sense amplifiers, each gate structure extending in the row direction.

Abstract: A method of making an image sensor includes depositing a shield layer over a substrate, wherein the substrate comprises a first photodiode (PD) and a second PD. The method further includes etching the shield layer to define a first recess aligned with the first PD and a second recess aligned with the second PD. The method further includes depositing a flicker reduction layer in the first recess and in the second recess. The method further includes etching the flicker reduction layer to remove the flicker reduction layer from the first recess.

Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.

Abstract: An automatic detection method for a paper size is disclosed. a plurality of mark points is set on a paperweight along a paperweight direction that is different from a feeding direction. The disclosure senses a plurality of row images combining into a scan image during a paper passing between the paperweight and an image sensor, determines an edge length of the paper based on a range of the mark points covered by the paper, and determines a paper size based on the edge length. The disclosure can effectively detect the paper size without any additional sensors.

Abstract: A device for adjusting the degree of tightness is provided. The device is for a first strap element and a second strap element. The device includes an outer adjustment element, an inner adjustment element, and an intermediate adjustment element. The inner adjustment element is disposed inside the outer adjustment element. The intermediate adjustment element is disposed between the inner adjustment element and the outer adjustment element. The first strap element includes a first hollow region, and the second strap element includes a second hollow region. The inner adjustment element passes through the first hollow region and the second hollow region to adjust the degree of overlapping of the first hollow region and the second hollow region.

Abstract: A foldable mechanism includes a first movable plate, a second movable plate and a linkage structure. The first movable plate is below and supports an object to be rolled. The second movable plate is spaced apart from the first movable plate along a first direction, is connected to a first end of the object to be rolled and is below and supports the object to be rolled. The linkage structure is movably connected between the first movable plate and the second movable plate. The first movable plate is configured to move along a second direction to drive the linkage structure to fold or unfold, and the linkage structure is configured to drive the second movable plate to move close to or away from the first movable plate along the first direction, so as to switch the object to be rolled between a rolled state and an unrolled state.

Abstract: Disclosed are compounds of formula (I) as follows: in which each of R1, R2, R3, R4, R5, L1, W, and Het is defined herein. Also provides are a method of inhibiting prostaglandin reductase 2 (“PTGR2”) using such a compound and a pharmaceutical composition containing same.

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Abstract: In one embodiment, a computing system may access color components of a pixel region in an image, and then determine a color variance for each of the color components. The computing system may further determine a desired bit allocation for each of the color components based on the color variance associated with that color component. The computing system may then determine a total bit allocation for the pixel region based on the desired bit allocations for the color components, as well as a number of unallocated bits available for allocation. The computing system may further determine a final bit allocation for each of the color components by allocating the total bit allocation to each of the color components according to the desired bit allocation for each of the color components. The computing system may then encode each of the color components using the associated final bit allocation.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: The disclosure provides a nozzle for combustion and reforming reaction including a fuel pipe, a reformer, an activation pipe, an activation catalyst, and a reformation catalyst. The fuel pipe includes an annular wall and an end wall connected to an end of the annular wall. The fuel pipe has at least one vent hole penetrating through the annular wall and at least one outlet penetrating through the end wall. The reformer is disposed in the fuel pipe. The activation pipe is disposed in the fuel pipe and disposed through the reformer. A distance between the activation pipe and the outlet is larger than a distance between the vent hole and the outlet. The activation catalyst is arranged in the activation pipe. The reformation catalyst is arranged in the reformer and located outside the activation pipe. The disclosure also provides a combustor and a fuel cell system having the nozzle.

Abstract: A power supply device, a power supply management module and method are provided. The power supply device includes a power supply management module. The power supply management module includes a first and a second power supply module, a detection unit, and a switching control module. The first power supply module includes a first alternating current input end, a first rectifier circuit, and a first switch unit. A first end of the first switch unit is connected to the first rectifier circuit. The second power supply module includes a second alternating current input end, a second rectifier circuit, and a second switch unit. A third end and a fourth end of the second switch unit are connected to the second rectifier circuit and a second end of the first switch unit, respectively. The switching control module controls the first and the second switch unit according to a detection signal.

Abstract: An image retrieval system receives an image for which to identify relevant images from an image repository. Relevant images may be of the same environment or object and features and other characteristics. Images in the repository are represented in an image retrieval graph by a set of image nodes connected by edges to other related image nodes with edge weights representing the similarity of the nodes to each other. Based on the received image, the image traversal system identifies an image in the image retrieval graph and alternatively explores and traverses (also termed “exploits”) the image nodes with the edge weights. In the exploration step, image nodes in an exploration set are evaluated to identify connected nodes that are added to a traversal set of image nodes. In the traversal step, the relevant nodes in the traversal set are added to the exploration set and a query result set.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: The present invention discloses a method for determining the stimulated reservoir volume of horizontal wells by coupling reservoir flow, comprising the following steps: establishing a reservoir grid based on the reservoir geological model of the target well and adding an initial fracture unit; calculating the stress intensity factor at the fracture tip, judging the fracture initiation and determining the total number of fracture units; calculating the fluid pressure of fracture units, the pore pressure distribution and water saturation distribution of the reservoir matrix and micro-fractures during hydraulic fracturing; working out the stimulated reservoir volume of the horizontal well according to the fracture parameters, pressure distribution and water saturation distribution in shale reservoirs. The present invention can simulate fracture propagation, fracturing fluid leak-off and reservoir fluid flow in the whole fracturing process, determine the stimulated reservoir volume of horizontal wells.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.