Abstract: An automotive seat rail includes a rail and an engaging structure. The engaging structure includes a fixing frame, an engaging member and an elastic member. The fixing frame includes a fixing portion and an abutting portion fixed to and abutting an inner rail respectively. The engaging member includes an engaging section, a base section, and a stress section sequentially coupled to each other and bent with respect to each other. The base section is pivotally coupled to the fixing frame, and the engaging section is engaged between the inner and outer rails. When the stress section is controlled by an external force, the engaging section is driven to release the engagement between the inner rail and the outer rail, so as to ensure the accurate action of the engaging structure and allow the engaging member to have better structural strength, smoother control, and more accurate engagement and disengagement effects.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: A portable surface finishing device based on coherent light source includes a cover, a laser source, an optical calibrating module and a laser scanning module. The cover includes a beam output opening. The laser source is disposed in the cover, and is for providing a laser beam. The optical calibrating module is disposed in the cover, and the laser beam passes through the optical calibrating module. The laser scanning module is disposed in the cover, and the laser beam from the optical calibrating module passes through the laser scanning module so as to linearly output on a target surface. The laser scanning module includes a multifaceted reflective structure, a rotation driving mechanism and an F-theta lens.

Abstract: An electric drive mechanism of a seat rail includes a front frame, a rear frame, a gear assembly, a lead screw and a bumper. The front frame and rear frame are separated from each other and fixed to an outer rail of a slide rail; the lead screw is spanned across the front frame and rear frame; the gear assembly driven by a driving device is fixed to an inner rail of the slide rail and engaged with the lead screw; the bumper is installed at the rear frame provide a buffering effect between the gear assembly and the rear frame, so as to prevent the production of abnormal sounds caused by colliding the gear assembly with the rear frame directly.

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a plurality of fins on a substrate, and a metal gate structure disposed on the plurality of fins. The metal gate structure includes a work function metal layer over the plurality of fins, a metal layer on the work function metal layer, and a metal oxide layer on the metal layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of tins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: A highlight processing method includes: obtaining a frame sequence that includes frames each having image contents associated with at least one object, wherein object pose estimation is performed upon each frame of the frame sequence to generate an object pose estimation result of each frame, and further includes determining at least one of a start point and an end point of a highlight interval, wherein comparison of object pose estimation results of different frames is involved in determination of at least one of the start point and the end point of the highlight interval.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: A pressure sensor and a display device are described. The pressure sensor includes a plurality of pressure units. Each of the pressure units includes four resistors having substantially the same resistance value. The four resistors form a Wheatstone bridge. Two resistors of the four resistors form a first resistor group. The other two resistors of the four resistors form a second resistor group. Orthogonal projections of electrodes of the two resistors of each of the resistor groups at least partially overlap in a direction perpendicular to a plane on which the pressure units are located. Extension directions of electrode patterns of the two resistors of each of the resistor groups are different.

Abstract: A mobile device enables a user to edit a video containing a human figure, such that an original human pose is modified into a target human pose in the video. In response to a user command, the mobile device first identifies key points of the human figure from a frame of the video. The user command indicates a target position of a given key point of the key points. The mobile device generates a target frame including the target human pose, with the given key point of the target human pose at the target position. An edited frame sequence is generated on the display including the target frame. The edited frame sequence shows the movement of the human pose transitioning into the target human pose.

Abstract: A light strip assembly includes a plurality of light strips in series connection. Each of the light strips includes a straight strip member, a light guiding member, and a light emitting device. The strip member has a mounting surface and an exit surface, and the light guiding member is connected to the mounting surface of the strip member and has an entrance surface and a reflector. The light emitting devices emit lights to the light guiding members via the entrance surfaces, and the lights are reflected by the reflectors to emit to the strip members, and then the lights leave the strip members via the exit surfaces.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A light strip assembly includes a plurality of light strips in series connection. Each of the light strips includes a straight strip member, a light guiding member, and a light emitting device. The strip member has a mounting surface and an exit surface, and the light guiding member is connected to the mounting surface of the strip member and has an entrance surface and a reflector. The light emitting devices emit lights to the light guiding members via the entrance surfaces, and the lights are reflected by the reflectors to emit to the strip members, and then the lights leave the strip members via the exit surfaces.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.