Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A computer-executable method for generating a side-by-side three-dimensional (3D) image includes the steps of creating a 3D mesh and estimating depth information of the raw image. The method further includes the steps of updating the left mesh area and the right mesh area of the 3D mesh based on the estimated depth information of the raw image and projecting each of the mesh vertices of the left mesh area onto a coordinate system of the side-by-side 3D image based on a left eye position, and projecting each of the mesh vertices of the right mesh area onto the coordinate system of the side-by-side 3D image based on a right eye position. The method further obtains the side-by-side 3D image by coloring the left mesh area and the right mesh area projected onto the coordinate system of the side-by-side 3D image based on the raw image.

Abstract: A method of measuring chip characteristics includes: outputting an operating voltage to a chip by a test device, wherein the chip comprises a plurality of oscillator circuits configured to generate a plurality of oscillating signals according to the operating voltage; and testing the chip by the test device under a situation that the test device outputs a system clock signal having a first clock period to the chip, including: changing the operating voltage sequentially with the test device until the chip changes from a normal state to a failure state, so as to generate a boundary operating voltage; and recording the plurality of oscillating signals generated according to the boundary operating voltage as measurement data by the test device, wherein the measurement data represents chip characteristics of the chip corresponding to the first clock period.

Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.

Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.

Abstract: A device for treating a user's skin using plasma is provided. The device comprises a plasma generation assembly and a power supply. The plasma generation assembly comprises a discharge electrode including a first surface; a first dielectric material layer provided on the first surface of the discharge electrode and the first surface, a ground electrode surrounding the discharge electrode, and an insulation member spacing around the discharge electrode from the ground electrode. The power supply configured to apply power to the plasma generation assembly so that plasma is generated from the first surface of the discharge electrode to the ground electrode and between the first dielectric material layer and the user's skin.

Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: A method for detecting and/or preventing overfitting in training of deep learning and neural network models. The method has a classifier-training method, an overfitting-detection method, and an overfitting-prevention method. The classifier-training method trains one or more classifiers using training histories and labels of one or more trained machine-learning (ML) models. The overfitting-detection method uses the trained classifiers based on the training history such as validation losses of a trained target ML model to identify an overfitting status of the trained target ML model. The overfitting-prevention method is performed during the training of a target ML model and uses the trained classifiers based on the training history of the target ML model to identify and preventing overfitting of the target ML model.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A backlight module including a light guide plate, a light source, an upper prism sheet, and a lower prism sheet is provided. The light guide plate has a light incident surface and a light emitting surface. The upper prism sheet is disposed at a side of the light emitting surface of the light guide plate. The upper prism sheet includes an upper substrate and first prism microstructures. Cross-sections of the first prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 80 to 90 degrees. The lower prism sheet is disposed between the light guide plate and the upper prism sheet. The lower prism sheet includes a lower substrate and second prism microstructures. Cross-sections of the second prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 100 to 130 degrees.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: Described methods and systems for achieving an optical bokeh effect by a camera supporting a computing device, such as a laptop computer. A measurement is performed as to focus spot position of a subject. The depth of field (DOF) of camera lens is determined. An offset as to the focus spot position is calculated such the background of the subject would be blurred to increase the optical bokeh effect. The offset is added to the focus spot position or to be more in focus to decrease optical bokeh in the background, to arrive at a focus spot position that supports the optical bokeh effect. The camera lens is adjusted for the new focus spot position.