Abstract: A LCD panel including an active device array substrate, an opposite substrate, a liquid crystal layer, a conductive sealant and restraining elements is provided. The active device array substrate includes common lines, transfer pads and a dielectric layer. The dielectric layer has openings exposing the transfer pads. The opposite substrate has a common electrode. The liquid crystal layer and the conductive sealant are disposed between the active device array substrate and the opposite substrate. The conductive sealant surrounds the liquid crystal layer. The openings are corresponding to corners of the conductive sealant. The conductive sealant fills the openings and the common electrode is electrically connected to the transfer pads through the conductive sealant. Further, the restraining elements are between the active device array substrate and the opposite substrate and are distributed around the corners of the conductive sealant such that the conductive sealant is forced to fill into the openings.

Abstract: The invention provides a method for forming a semiconductor structure. A substrate is provided. A conductive layer is formed on the substrate. A first patterned mask layer is formed on the conductive layer. The conductive layer exposed by the first patterned mask layer is removed to expose a first sidewall of the conductive layer. A doped region is formed in the substrate by a doping step using the first patterned mask layer as a mask. The first patterned mask layer is removed. A second patterned mask layer is formed on the conductive layer. The conductive layer exposed by the second patterned mask layer is removed to expose a second sidewall opposite to the first sidewall of the conductive layer. The second patterned mask layer is removed.

Abstract: An exemplary display panel includes a plurality of monochrome pixels, a plurality of data lines and a plurality of control lines. Each monochrome pixel provides a specific color on the display panel. The data lines are electrically coupled to the monochrome pixels for providing the display data. The data lines includes a first data line electrically coupled to a part of the monochrome pixels, and the specific colors provided by the part of the monochrome pixels are of the same color. Besides, each of the control lines is electrically coupled to a part of the monochrome pixels for controlling the part of the monochrome pixels electrically coupled thereto whether to receive the display data from the data lines.

Abstract: A method for controlling gate signals of a liquid crystal display (LCD), including generating gate signal with a modulated pulse width according to the gate signal with a default pulse width; when the LCD is booting up, outputting the gate signal with the modulated pulse width; and when a backlight module of the LCD is turned on, switching the gate signal with the modulated pulse width to the gate signal with the default pulse width. This way, the pulse width of the gate signal is increased after the LCD is boot up and before the backlight module is turned on, enabling the LCD to be boot properly in low temperature, without the need to raise the voltage level of the gate signal.

Abstract: Exemplary backlight driving method and display device are provided. The display device includes a light source array. The light source array includes a first group of light-emitting rows and a second group of light-emitting rows. The backlight driving method includes the steps of: firstly, receiving a gate driving frequency of the display device; subsequently, generating a backlight driving frequency according to the gate driving frequency; and afterwards, sequentially providing a first row driving voltage to the first group of light-emitting rows in a first time period and sequentially providing a second row driving voltage to the second group of light-emitting rows in a second time period, according to the backlight driving frequency. The first time period and the second time period have different phases from each other, and the gate driving frequency is different from the backlight driving frequency.

Abstract: A method for manufacturing a bicycle rim includes the following steps. A first bar of material and a second bar of material are formed by extrusion. The first bar and the second bar are respectively made into an arched section of material (unfinished external ring, unfinished internal ring) and cut. Excessive portions of the unfinished external and internal rings are cut from by trimming. The unfinished external and internal rings are assembled and interconnected to each other. The assembled unfinished external and internal rings are laterally pressed to promote a connection between the unfinished external and internal rings. The ends of the unfinished external ring are welded and connected to each other, and the ends of the unfinished internal ring are welded and connected to each other to from a rim structure. Any roughness of the rim structure is ground and the bicycle rim is finished.

Abstract: The invention provides a method for forming a semiconductor structure. A substrate is provided. A conductive layer is formed on the substrate. A first patterned mask layer is formed on the conductive layer. The conductive layer exposed by the first patterned mask layer is removed to expose a first sidewall of the conductive layer. A doped region is formed in the substrate by a doping step using the first patterned mask layer as a mask. The first patterned mask layer is removed. A second patterned mask layer is formed on the conductive layer. The conductive layer exposed by the second patterned mask layer is removed to expose a second sidewall opposite to the first sidewall of the conductive layer. The second patterned mask layer is removed.

Abstract: Deep trench isolation structures between high voltage semiconductor devices and fabrication methods thereof are presented.

Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.

Abstract: A rim includes an external ring and an internal ring. The external ring includes two walls each including a brake-contacting face, a middle portion interconnecting the walls, a bead-receiving groove defined by the walls and the intermediate portion, two external flanges extending from the middle portion opposite to the walls, two internal flanges extending from the middle portion opposite to the walls. An edge-receiving groove is defined between each of the external flanges and a related one of the internal flanges. The internal ring includes two walls and an intermediate portion interconnecting the walls. Each of the walls of the internal ring includes an edge inserted in a related one of the edge-receiving grooves, a shoulder abutted against. a related one of the external flanges, and an external side in flush with the brake-contacting face of a related one of the walls of the external ring.

Abstract: A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

Abstract: A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.

Abstract: A liquid crystal display and a shift register unit thereof are provided. The shift register unit includes a first switch, a second switch, and a level shift circuit. The first switch has a first input terminal, a first control terminal, and a first output terminal. The second switch has a second input terminal, a second control terminal, and a second output terminal. The second control terminal is coupled to the first output terminal and the level shift circuit. When the first switch is enabled, the first input terminal receives an input signal converting the voltage of the second control terminal into a first voltage for turning on the second switch. The second output terminal outputs a first clock signal to a scan signal line. When the level shift circuit is enabled, the voltage of the second control terminal is converted into a second voltage for turning off the second switch.

Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

Abstract: A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

Abstract: A control circuit equipped with electrostatic discharge (ESD) protection includes a plurality of shift registers, a plurality of buses coupled to the plurality of shift registers, a common line, a set of ESD protection components coupled to a set of the plurality of the buses for protecting the plurality of buses from ESD events; and a set of current paths coupled between the set of the ESD protection components and the common line for providing the ESD current paths to pass through.

Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.

Abstract: A liquid crystal display and a shift register unit thereof are provided. The shift register unit includes a first switch, a second switch, and a level shift circuit. The first switch has a first input terminal, a first control terminal, and a first output terminal. The second switch has a second input terminal, a second control terminal, and a second output terminal. The second control terminal is coupled to the first output terminal and the level shift circuit. When the first switch is enabled, the first input terminal receives an input signal converting the voltage of the second control terminal into a first voltage for turning on the second switch. The second output terminal outputs a first clock signal to a scan signal line. When the level shift circuit is enabled, the voltage of the second control terminal is converted into a second voltage for turning off the second switch.