Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. The dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. The dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. By including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.

Abstract: Various embodiments described herein may relate to apparatuses, systems, techniques, and/or processes that are directed to tunable lasers. Specifically, embodiments herein may relate to chips that include both a tunable laser portion as well as a WLL portion on a same silicon substrate. Other embodiments may be described and/or claimed.

Abstract: An embedded device package substrate includes a line board including a first insulating layer and a first line layer located on an upper surface of the first insulating layer, a core layer covering the first line layer and including a preset opening, a device embedded in the preset opening, a packaging layer covering the core layer and filling the gap between the core layer and the device, and an outer line layer located on the packaging layer. The outer line layer is connected to a terminal of the device by a first conductive column penetrating through the packaging layer and to the first line layer by a second conductive column penetrating through the core layer and the packaging layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Abstract: A display panel and a display device is provided in the present disclosure, which belongs to the field of display technologies. The display panel includes a base substrate and a plurality of pixel circuits disposed on the base substrate. At least two pixel circuits in a same column are coupled with a same first initial power line, such that only a small quantity of signal lines need to be disposed on the base substrate. Accordingly, an area which needs to be occupied by the signal lines and is of the base substrate becomes smaller, thereby facilitating high-resolution design of the display panel.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.

Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.

Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

Abstract: A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.

Abstract: In one embodiment, a method includes rendering, for one or more displays of a VR display device, a first output image of a VR environment based on a field of view of a first user. The method includes determining whether a second user is approaching within a threshold distance of the first user and outside the field of view of the first user. The method includes rendering, responsive to determining the second user is approaching within the threshold distance of the first user and outside the field of view of the first user, for the one or more displays of the VR display device, a second output image comprising a directional warning. The directional warning may indicate a direction of movement of the second user relative to the first user.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: An electronic device displays a first user interface; receives a first operation of a user; obtains first content of the first user interface in response to the first operation; displays a second user interface, where content displayed in the second user interface includes a text in the first content, and the second user interface covers a part of a display area of the first user interface; reads a first sentence in the content of the second user interface; and displays marking information of a text that is in the second user interface and that corresponds to the first sentence that is being read. Embodiments of this application are used for text reading.

Abstract: A mechanical lock is used for a charging connector. The charging connector includes a housing and a hook. The hook has an engaging portion and an operating portion. The mechanical lock includes a push rod, a swing lever and a first elastic member. The push rod is slidably arranged on the housing along a first direction. The push rod has a heart-shaped cam and a heart-shaped groove. The heart-shaped groove has an unlocking position and a locking position. When an end of the swing lever is located at the locking position, the operating portion is locked by the push rod, and the operating portion cannot move. When the end of the swing lever is located at the unlocking position, the push rod unlocks the operating portion, and the operating portion is movable.

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: Described herein are surface treatment methods for removing one or more surface defect layers from polycrystalline films, polycrystalline films that are free of one or more defect surface layers, and use of the films in solar cells. In certain embodiments, the method is conducted by means of an adhesive tape or mechanical polishing. As described herein, solar cells containing the surface treated perovskite films show enhanced efficiency and stability.

Abstract: An ammonia fuel cell system capable of rapid adsorption-and-desorption switching by ammonia self-evaporation includes an ammonia decomposition reactor; an ammonia tank; a first heat exchanger; a fuel tank; a first blower; a second heat exchanger; an adsorption column device; a fuel cell; a gas circulation system; and an exhaust gas combustion system, wherein an outlet of the ammonia tank connects with an ammonia gas inlet of the ammonia decomposition reactor, wherein a decomposition gas outlet of the ammonia decomposition reactor, through the first heat exchanger, connects with an adsorption inlet of the adsorption column device, wherein a product produced by decomposition of ammonia gas in the ammonia decomposition reactor preheats a raw ammonia gas via the first heat exchanger, wherein the fuel tank connects with the ammonia decomposition reactor for feeding a fuel gas to the ammonia decomposition reactor.