Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.

Abstract: A display panel including pixel circuits each including a drive transistor and a first reset transistor; first signal line including an indirect-connection signal line and a direct-connection signal line; connection signal lines, at least part of which is electrically connected to the indirect-connection signal lines; anodes; a pixel circuit group including two pixel circuits at least partially symmetric and adjacent, the first reset transistors of two pixel circuits being adjacent to each other, and adjacent first reset transistors being connected through a first semiconductor connection line, which is connected to the reset signal line; and pixel columns, two sides of the drive transistors in a pixel column being provided with two first signal lines and two second connection signal lines. At least part of the anodes overlaps with adjacent first signal lines and/or two adjacent second connection signal lines.

Abstract: The present disclosure pertains to the field of back contact heterojunction cell technologies, and particularly relates to a mask-layer-free hybrid passivation back contact cell and a fabrication method thereof; the method includes: S101: providing a silicon wafer substrate; S102: sequentially forming a first semiconductor layer and a mask layer on a back surface of the silicon wafer substrate, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S103: performing first etching on the first semiconductor layer on the obtained back surface to form first opening regions W1; S104: forming a textured surface in the first opening region W1 on the back surface by texturing and cleaning; S105: removing the mask layer; S106: forming a second semiconductor layer on the obtained back surface; and S107: performing second etching on a polished region of the obtained back surface.

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Abstract: A light-emitting device includes a substrate, multiple light-emitting units that are disposed on the substrate, that are spaced apart by an isolation trench and that are and electrically interconnected by an interconnecting structure, and an insulating layer with thickness of 200 nm to 450 nm. A potential difference between adjacent two light-emitting units not in direct electrical connection is at least two times forward voltage of each of the light-emitting units. Each light-emitting unit includes a light-emitting stack and a light-transmissible current spreading layer. The insulating layer covers the light-transmissible current spreading layers and at least a part of the light-emitting stacks.

Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of signal lines and a plurality of units. The signal lines are disposed on the substrate. The units are disposed on the substrate. At least one of the units includes a first main pad, a first redundant pad, and an electronic component including a first electrode. In addition, one of the signal lines is electrically connected to the first electrode of the electronic component, the first main pad and the first redundant pad.

Abstract: A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.

Abstract: An insulator for an ion implantation source may provide electrical insulation between high voltage components and relatively lower voltage components of the ion implantation source. To reduce the likelihood of and/or prevent a leakage path forming along the insulator, the insulator may include an internal cavity having a back and forth pattern. The back and forth pattern of the internal cavity increases the mean free path of gas molecules in the ion implantation source and increases the surface area of the insulator that is not directly or outwardly exposed to the gas molecules. This results in a continuous film or coating being more difficult and/or less likely to form along the insulator, which extends the working time of the ion implantation source.

Abstract: A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.

Abstract: Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.

Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

Abstract: A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer.

Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.

Abstract: Aspects of the disclosure provide methods and apparatuses. The method can include receiving, at a user equipment (UE), system information broadcast from one or more base stations which may be shared by one or more PLMNs and/or one or more SNPNs, the system information including an indication of whether accessing an SNPN using home service provider (HSP) subscription of a HSP network is supported. The UE can be configured with subscription information of the HSP network. The subscription information can include the HSP subscription and a selection list that includes one or more candidate networks each represented by an SNPN identifier. The method can further include responsive to the system information, selecting a network from the selection list according to a priority order of the candidate networks, and accessing the network selected from the selection list using the HSP subscription.

Abstract: Provided are an authentication processing method and device, a storage medium, and an electronic device. The method includes that: a terminal receives an authentication request message from an authentication function; and in cases where authentication on the authentication request message fails, the terminal feeds back an authentication failure message to the authentication function. In cases where the cause of the authentication failure is a Message Authentication Code (MAC) failure and in cases where a cause of authentication failure is a Synchronization (Sync) failure, the terminal feeds back authentication failure messages of the same type to the authentication function.

Abstract: Disclosed is an electrolytic aluminum system based on a flexible DC (Direct Current) microgrid, by using the current adjustment and cloud monitoring transmission technology for electrolytic aluminum temperature electrochemical reaction elements.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

Abstract: An electrochemical plating apparatus for performing an edge bevel removal process on a wafer includes a cell chamber. The cell chamber includes two or more nozzles located adjacent to the edge of the wafer. A flow regulator is arranged with each of the two or more nozzles, which is configured to regulate an tap width of a deposited film flowing out through the each of the two or more nozzles. The electrochemical plating apparatus further includes a controller to control the flow regulator such that tap width of the deposited film includes a pre-determined surface profile. The two or more nozzles are located in radially or angularly different dispensing positions above the wafer.