Abstract: A battery cell appearance defect detection apparatus may comprise: a first detection assembly comprising a first image collector and a first light source, wherein the first light source emits first light, the first light forming a first included angle with a detection surface, and the first image collector collects a first image of the position on the battery cell irradiated by the first light; a second detection assembly comprising a second image collector and a second light source, wherein the second light source emits second light, the second light forming a second included angle with the detection surface, and the second image collector collects a second image of the position on the battery cell irradiated by the second light, with the second included angle being less than the first included angle; and a control assembly constructed to detect appearance defects of the battery cell.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: Provided is a metal-oxide thin-film transistor. The metal-oxide thin-film transistor includes a gate, a gate insulation layer, a metal-oxide semiconductor layer, a source electrode, a drain electrode, and a passivation layer that are successively disposed on a base substrate; wherein the source electrode and the drain electrode are both in a laminated structure, wherein the laminated structure of the source electrode or the drain electrode at least includes a bulk metal layer and an electrode protection layer; wherein the electrode protection layer includes a metal or a metal alloy; the electrode protection layer is at least disposed between the metal-oxide semiconductor layer and the bulk metal layer; wherein a metal-oxide layer is disposed between the electrode protection layer and the bulk metal layer.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Abstract: Some embodiments relate to an integrated chip including a semiconductor substrate and a pixel array comprising a plurality of photodetectors in the semiconductor substrate. The pixel array further comprises a plurality of transistors on a frontside of the semiconductor substrate. A backside ground (BSGD) structure extends into a backside of the semiconductor substrate, opposite the frontside, and further surrounding the pixel array along a periphery of the pixel array. The BSGD structure has a first sloped sidewall extending from a bottom surface of the BSGD structure that is recessed into the semiconductor substrate.

Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.

Abstract: The present invention provides a light-emitting diode structure, comprising a substrate, a first semiconductor layer, a second semiconductor layer, a second electrode and at least one current blocking trench. The substrate includes a first electrode. The first semiconductor layer is located on the substrate. The second semiconductor layer is located on the first semiconductor layer, and a light-emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The second electrode is located on the second semiconductor layer. Each current blocking trench is recessed from a light exit surface of the second semiconductor layer toward the substrate. By means of the at least one current blocking trench, the current flowing from the second electrode flows through the light-emitting layer located outside the second electrode to the first electrode in a diffusing manner.

Abstract: The present application provides a positive electrode active material and the preparation thereof, a secondary battery, a battery module, a battery pack, and electrical device. The positive electrode active material of the present application comprises a layered sodium composite oxide containing antimony having a chemical formula of Formula I, NaxMnaFebNicSbdLeO2 (I), in which 0.7<x?1, 0<a, 0?b, 0.1<c?0.3, 0<d?0.1, 0?e, a+b+c+d+e=1, (b+c)/(a+d+e)?1, and L is one or more selected from Cu, Li, Ti, Zr, K, Nb, Mg, Ca, Mo, Zn, Cr, W, Bi, Sn, Ge, Al, Si, La, Ta, P, and B. The layered sodium composite oxide containing antimony of the present application, by being doped with specific metal Sb, has high stability to water.

Abstract: Methods and OLED devices are provided in which organic emissive materials are deposited over a substrate via OVJP print heads in a continuous line extending from one edge of the active display portion of a substrate to another. The print heads are arranged such that the sidewalls of the OVJP jet are disposed over non-emissive insulating portions of the display panel, thereby allowing for improved pixel density and resolution in comparison to conventional OVJP and similar techniques.

Abstract: The light emitting diode packaging structure includes a flexible substrate, micro light emitting elements disposed on the flexible substrate, a conductive pad, a redistribution layer, and an electrode pad. The micro light emitting elements have a first surface facing to the flexible substrate and a second surface opposite to the first surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting elements. The redistribution layer covers the micro light emitting elements and the conductive pad. The redistribution layer includes an insulating layer and a circuit layer embedded in the insulating layer. The circuit layer is electrically connected to the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer.

Abstract: A micro light-emitting diode display is based on a conventional micro light-emitting diode display and includes at least one electrically conductive material layer or at least one functional material added to an encapsulation layer, so as to achieve antistatic effect. The micro light-emitting diode display solves the problem that the conventional micro light-emitting diode display is easily damaged by electrostatic breakdown.

Abstract: A primary controller applied to a primary side of a power converter includes a current peak upper limit adjustment circuit and a gate control signal generation circuit. The current peak upper limit adjustment circuit increases a current peak upper limit of the primary side of the power converter when a gate control signal is enabled at a second valley of a voltage, and reduces the current peak upper limit when the gate control signal is enabled at an Nth valley of the voltage, wherein N is a positive integer. The gate control signal generation circuit is coupled to the current peak upper limit adjustment circuit, wherein the gate control signal generation circuit enables the gate control signal, disables the gate control signal according to the current peak upper limit, and the gate control signal is used for turning on a power switch of the primary side of the power converter.

Abstract: An example method may include receiving, at a device, a first frame over a wireless network and constructing a preliminary data portion of a second frame. The second frame may be configured for transmission over the wireless network. The method may also include in response to the receiving of the first frame at the device, beginning transmission of a header portion of the second frame over the wireless network and after the beginning transmission of the header portion of the second frame, constructing, based on the preliminary data portion, a finalized data portion of the second frame for transmission over the wireless network.

Abstract: The present disclosure provides a direct drive transmission system and a control method. The direct drive transmission system includes: a base plate, guide rails, a plurality of stators, a mover, a first position feedback device, a plurality of second position feedback devices, a plurality of drivers, and a controller. The first position feedback device aligns with a respective second position feedback device. The plurality of stators are configured to drive the mover to slide on the guide rails. The plurality of second position feedback devices are arranged at intervals and are electrically connected to the controller. The controller is configured to control driving operations of the plurality of drivers according to effective position information fed back by the plurality of second position feedback devices.

Abstract: A compact tunable optical true time delay consists of an optical subassembly to apply dispersion-free time delay to the input optical signal, and a mechanical subassembly to facilitate tuning the delay using a linear actuator. The deployment of a precision optical ferrule sliding in a precision split sleeve offers a self-contained and inexpensive method to minimize optical misalignment during the tuning process, which releases the burden of the mechanical subassembly and is also advantageous in keeping the device compact. The exterior dimension remains unchanged at any moment despite the interior motion. Both reflection-type and transmission-type optical time delays are introduced, driven either manually or electrically.

Abstract: The present invention discloses a cylindrical impact linear motor and a manufacturing method therefor. A cylindrical impact linear motor includes a main housing and a vibrator assembly arranged in a central cavity. The main housing is provided with two anti-collision structures. The vibrator assembly includes two strong magnetic strips which are axially connected in series to each other and have poles with the same polarity adjacent to each other, and a magnetic isolation member arranged between the two strong magnetic strips. The cylindrical impact linear motor further includes an electromagnetic coil embedded in the main housing and located on an outer periphery of the vibrator assembly. The direction and magnitude of a current conducted by the electromagnetic coil are changed to form an axial movement of the vibrator assembly in proportion to the change of the current, thereby forming an impact frequency and an impact force in proportion.

Abstract: The present invention provides a multi-port charging circuit, a device, and a control method. The circuit includes: a main power supply module, a control module, a detection module, N backup power supply modules, and N power supply ports; each power supply port is connected to an output end of the main power supply module through a switch respectively; each backup power supply module is connected to the corresponding power supply port respectively. When a device is connected to the corresponding power supply port, power is supplied by the corresponding backup power supply module. Only when the power value required by the connected device exceeds the power supply capacity range of the corresponding backup power supply module, the main power supply module supplies power to the corresponding power supply port. The present invention ensures the normal charging of low-power devices while maximizing the implementation of fast charging functions of other ports.