Abstract: A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

Abstract: One embodiment includes a surgical wound closure device comprising a substrate having a proximal surface and a distal surface; a drape having a proximal surface and a distal surface, and being disposed proximally to said substrate; and an adhesive layer having a proximal surface and a distal surface; said drape being disposed releasably adherently to said distal surface of said adhesive layer.

Abstract: One embodiment includes a surgical wound closure device comprising a substrate having a proximal surface and a distal surface; a drape having a proximal surface and a distal surface, and being disposed proximally to said substrate; and an adhesive layer having a proximal surface and a distal surface; said drape being disposed releasably adherently to said distal surface of said adhesive layer.

Abstract: A non-volatile lubricious coating composition is provided for use with medical devices, such as hypodermic needles, catheters, and the like. The coating composition includes a first siloxane polymer having a very low viscosity less than about 50 centistokes, a second siloxane polymer having a high viscosity greater than about 1,000 centistokes, a reactive silicone polymer which is capable of crosslinking upon exposure to radiation, such as a UV curable silicone acrylate, and a photoinitiator to accelerate cross-linking of the reactive silicone polymer. The coating composition may further include an aminofunctional siloxane polymer to promote adhesion to metal surfaces when used with needles. The coating composition provides flowability without the need for any volatile organic solvent, and is capable of curing to provide adhesion and lubricity.

Abstract: A process for reducing the dark current generation of an image sensor cell, fabricated on a semiconductor substrate, has been developed. The process features the use of polysilicon pad structure, formed simultaneously with a polysilicon gate structure of a reset transistor, with the polysilicon pad structure located overlying, and contacting, a portion of the top surface of the photodiode element, of the image sensor cell. A small diameter opening, in a composite polysilicon-silicon oxide layer, exposes the portion of photodiode element to be contacted by the polysilicon pad structure. The small diameter opening is created using a procedure which allows the surface of the photodiode element, exposed in the small diameter opening to experience only a minimum of RIE processing at end point, thus minimizing damage to the surface of the photodiode element, and thus reducing dark current generation.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures, with an extended region for source drains bordering photodiode regions. Ions are implanted to form photodiodes, overlapping the extended bordering source drain regions. A blanket transparent insulating layer is deposited.

Abstract: A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

Abstract: In one embodiment, the present invention relates to a substrate for an electrical device including a coating, wherein the coating comprises an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In another embodiment, the present invention relates to a component for an electrical device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In yet another embodiment, the present invention relates to a microelectronic device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor.

Abstract: In one embodiment, the present invention relates to a substrate for an electrical device including a coating, wherein the coating comprises an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In another embodiment, the present invention relates to a component for an electrical device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In yet another embodiment, the present invention relates to a microelectronic device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor.

Abstract: In one embodiment, the present invention relates to metal oxide sols comprising a liquid and a polycondensation product of about 2 to about 5,000 monomers of a partially hydrolyzed chelated metal oxide precursor. In another embodiment, the present invention relates to a process for making a metal oxide sol comprising contacting a metal oxide precursor with a multifunctional compound in a liquid to provide a chelated metal oxide precursor; contacting the chelated metal oxide precursor with a hydrolyzing agent to provide partially hydrolyzed chelated metal oxide precursor monomers; and permitting the partially hydrolyzed chelated metal oxide precursor monomers to polycondense thereby forming a metal oxide sol.

Abstract: A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

Abstract: In one embodiment, the present invention relates to a substrate for an electrical device including a coating, wherein the coating comprises an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In another embodiment, the present invention relates to a component for an electrical device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In yet another embodiment, the present invention relates to a microelectronic device comprising an oxygen plasma resistant polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor.

Abstract: In one embodiment, the present invention relates to a polymer prepared from a mixture containing a polymerization material and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor. In another embodiment, the present invention relates to a process for making a polymer involving contacting a polymerization material with a metal oxide sol comprising a liquid and a polycondensation product of a partially hydrolyzed chelated metal oxide precursor to form a mixture and at least one of polymerizing and curing the mixture of the polymerization material and the polycondensation product.

Abstract: A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.

Abstract: A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Abstract: A process for providing a metal oxide-containing coating on a compatible substrate, the coating being transparent to a photocuring source output and upon cure being resistant to electrical stress. The process of the invention comprises a) preparing a precursor composition comprising a mixture of a stabilizer and a metal oxide sol precursor material; b) combining the stabilizer/metal oxide sol precursor material mixture with a photocurable base resin without high shear mixing to achieve a homogeneous, transparent composition; c) coating the substrate material with the transparent composition; and d) photocuring the coated substrate bearing the transparent composition, wherein the cured coating is homogenous and transparent and remains transparent in the use state, thereby rendering the coating corona resistant. This invention further relates to the coated substrate.

Abstract: A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions.

Abstract: A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.

Abstract: A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer.