Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

Abstract: A user mobile device includes a network interface, an input/output (“I/O”) device configured to exchange data with a user, the I/O device including a display device configured to present a graphical user interface to the user, an imaging device configured to generate image data; and a processing circuit. The processing circuit comprising a memory and a processor. The memory stores instructions that cause the processor to receiver user photograph data including multiple photographs of the user, determine an emotive state of the user in each of the photographs, categorize each photograph into at least a user positive emotion category and a user negative emotion category, receive spending behavior data, generate a user spending alert based on the spending behavior data including a photograph from at least one of the user positive emotion category and the user negative emotion category, and present the spending alert to the user.

Abstract: A system and method for preventing the double-spending of digital currency that transfers between multiple DLT networks. The system and method includes creating, based on a unit of fiat currency, a first digital currency of a first type on a first DLT network and a second digital currency of a second type on a second DLT network. Each of the first digital currency and the second digital currency simultaneously represent a value associated with the unit of fiat currency. The system and method includes detecting a transaction request to transfer the first digital currency from the first DLT network to the second DLT network. The system and method include locking, responsive to detecting the transaction request, the first digital currency onto the first DLT network to prevent a transfer of the first digital currency from the first DLT network to another DLT network responsive to a subsequent transaction request.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

Abstract: A process (100) for the recovery of solvent (1) from solvent-containing cellulosic particles (2) is shown, the process comprising the steps: a) extracting the solvent (1) from the cellulosic particles (2) by means of a liquid extraction medium (3), thereby obtaining a solvent-enriched extraction medium (5), and b) obtaining the recovered solvent (6) from the solvent-enriched extraction medium (5). In order to improve the efficiency of the process, it is proposed that in step a) the solvent (1) is extracted from the cellulosic particles (2) in a continuous flow extraction reactor (4), wherein the extraction medium (3) continuously flows through the extraction reactor (4) to extract the solvent (1) from the cellulosic particles (2).

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.

Abstract: The invention proposed the thermal imaging radar includes of main components: Assembly pedestal, Assembly rotary shaft, and Assembly housing. Electronic circuits, encoders, mechanisms, motor are optimized arranged and scientifically designed the layout space and the weight of the structure. This device is compact for camouflage purposes, easy to assemble or disassemble, and waterproof. The invention's products can be applied in automatic security station, produces 360-degree panoramic imaging of the continuously day and night for surveillance area, detects and tracks moving objects captured by the thermal sensor. Furthermore, The product is also applicable for monitoring the ambient temperature in large areas, localizing high-temperature areas to recognize and warn the possible explosions.

Abstract: A device for implanting a heart prosthesis including a central body, a containment portion having one or more sub-components, and a release device for the central body capable of being inserted into a catheter. A device for assisting the connection operation between the central body and the sub-components of the containment portion includes an assembly of catheters, of which there are at least two catheters for each sub-component of the containment portion, the catheters being joined to each other over a portion thereof and having at least one free end for each catheter.

Abstract: A monolithic ceramic capacitor has a plurality of dielectric layers and a plurality of conductive layers sintered together to form a substantially monolithic ceramic body. The ceramic body defines at least one void between the dielectric and conductive layers. The void is at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer. Within the dielectric body, the first and second conductive layers are connected in a nonconductive manner.

Abstract: Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.

Abstract: A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for structuring and training a recurrent neural network. This describes a technique that improves the ability to capture long term dependencies in recurrent neural networks by adding an unsupervised auxiliary loss at one or more anchor points to the original objective. This auxiliary loss forces the network to either reconstruct previous events or predict next events in a sequence, making truncated backpropagation feasible for long sequences and also improving full backpropagation through time.