Patents by Inventor An Trinh

An Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220358162
    Abstract: A method for providing automated customer feedback monitoring in real-time to facilitate identification and resolution of errors is disclosed. The method includes ingesting, via an application programming interface, data from a source, the data including feedback information from a customer; persisting the data in a file format, the file format including a tabular file format; filtering the persisted data based on a rating and a keyword; identifying a category for the filtered data based on a characteristic of the filtered data; determining whether a log file corresponds to the filtered data based on the identified category, the log file including an error log file that corresponds to an issue, and when the log file corresponds to the filtered data; correlating the filtered data with the determined log file; and determining a priority level for the issue by using the correlated data and the log file.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 10, 2022
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Manjunath VENUGOPALA REDDY, Veena N SINDGI, Jason BOCZ, Jessica Claire DUGGAN, Van Trinh NGUYEN
  • Publication number: 20220359604
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Chun-Kai Lan, Hai-Dang Trinh, Hsun-Chung Kuang
  • Publication number: 20220359823
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20220350585
    Abstract: Provided are a computer program product, system, and method for applying a code update to a target system from a personal communication device. A code update command is received from a messaging application, executing on the personal communication device of the user, indicating a code update to install on the target system a code update maintained in the target system. The code update command is processed to extract indication of the code update to install and a target system user identifier of the target system on which to install the code update. At least one job is generated to install the code update on the target system. The at least one job is transmitted to the target system to cause the target system to process the at least one job to install the code update.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Michael KOESTER, Kevin L. MINER, Trinh NGUYEN, Camvu PHAM
  • Publication number: 20220349045
    Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Shing-Chyang Pan
  • Publication number: 20220351766
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 3, 2022
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 11489112
    Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
  • Patent number: 11486486
    Abstract: A transmission includes a bar supporting at least one sensor for measuring an operating parameter of the transmission. The sensor bar is provided with an oil channel for transportation of lubrication oil to at least one component of the transmission.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 1, 2022
    Assignee: NINGBO GEELY AUTOMOBILE RESEARCH & DEVELOPMENT CO.
    Inventors: Freddy Trinh, HÃ¥kan Jacobson, Daniel Haraldsson
  • Publication number: 20220343403
    Abstract: Methods and systems for protecting seller privacy during an ecommerce transaction are disclosed. In one aspect, a method includes, receiving, via an online listing configuration interface for a first session, one or more candidate pick up times and specific pick up locations for an item, determining a generalized version of the one or more specific pick up locations, displaying, via a second session, an online listing for the item, displaying, via the second session, the one or more candidate pick up times and the generalized versions of the one or more specific pick up locations, receiving, via the second session, a selection of one of the candidate pick up times and one of the generalized versions of one of the specific pick up locations, in response to receiving payment for the item, displaying a specific pick up location corresponding to the selected one generalized version.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Hieu Van Nguyen, Huy Quang Nguyen, Tuan Thanh Phan, Hoang Trinh
  • Patent number: 11479849
    Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Shing-Chyang Pan
  • Patent number: 11482668
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Patent number: 11481035
    Abstract: System and method for managing a user interface for a foldable device are disclosed. The method includes: determining a folding state of the foldable device based on a folding angle of the foldable device; detecting an input gesture on one or more touch-sensitive display segments of a flexible display screen of a foldable device; determining a gesture type corresponding to the detected input gesture; determining whether the detected input gesture is a valid gesture or invalid gesture; and responsive to determining that the detected input gesture is a valid gesture, providing the gesture type corresponding to the detected gesture, the folding state of the foldable device, and display information to a software application or an operating system of the foldable device.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 25, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Thu Ha Trinh, Wei Li, Jin Tang, Marcello Giordano, Ghazaleh Saniee-Monfared, Chenhe Li, Siwen Yang, Zhou Xuan
  • Publication number: 20220336011
    Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.
    Type: Application
    Filed: July 4, 2022
    Publication date: October 20, 2022
    Inventors: Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Publication number: 20220336739
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Publication number: 20220336010
    Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Publication number: 20220336737
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 11477345
    Abstract: A printing device is implemented to activate a hidden function by inputting tap sequences on a tap screen. The hidden function includes displaying an icon of a title of a secret document on a display screen without showing the content of the secret document. A method for activating the hidden function using tap sequences is also disclosed. The method compares the input tap sequences with a plurality sets of predetermined codes, each of which corresponds to a hidden function. When the input tap sequences match one set of predetermined codes, the method activates and executes the hidden function. By executing the hidden function, the secret document is printed. The tap sequences are tapping actions that do not generate tangible symbols that are reviewable on the tap screen. By doing so, the confidential document is further protected.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 18, 2022
    Assignee: Kyocera Document Solutions Inc.
    Inventors: Matthew Trinh, Justine Lo, Jin Liang, Tai Yu Chen, Michael Ong Martin
  • Patent number: 11476416
    Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode over the bottom electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the top electrode and the switching layer. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Fa-Shen Jiang, Hsing-Lien Lin, Chii-Ming Wu
  • Publication number: 20220328292
    Abstract: A method of depositing a layer on a semiconductor workpiece is disclosed. The method includes placing the semiconductor workpiece on a wafer chuck in a processing chamber, introducing a first precursor into the processing chamber, introducing a second precursor into the processing chamber, and while the second precursor is in the processing chamber, applying radiation to the semiconductor workpiece, whereby a surface of the semiconductor workpiece is heated. The method also includes, while the second precursor is in the processing chamber, applying a voltage bias to the wafer chuck.
    Type: Application
    Filed: July 29, 2021
    Publication date: October 13, 2022
    Inventors: Hai-Dang Trinh, Hsun-Chung Kuang, Fa-Shen Jiang
  • Publication number: 20220319619
    Abstract: Circuitry and methods are disclosed for compensating for leakage in analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 6, 2022
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do