Patents by Inventor An-Yu Hsieh

An-Yu Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130245161
    Abstract: A resin composition includes (A) 100 parts by weight of epoxy resin; (B) 20 to 100 parts by weight of polybutadiene styrene divinylbenzene graft terpolymer resin; (C) 2 to 20 parts by weight of di-tert-butylhydroquinone (DTBHQ); (D) 5 to 50 parts by weight of polyphenyl ether modified cyanate ester resin; and at least one of (E) inorganic filler, (F) chain extending sealing agent, and (G) catalyst. The resin composition is characterized by specific ingredients and proportions thereof to attain high heat resistance, low dielectric constant Dk, and low dielectric dissipation factor Df, and being halogen-free, and therefore is applicable to protective film of printed circuit boards, insulating protective film of electronic components, and resin insulation film of leadframes.
    Type: Application
    Filed: December 28, 2012
    Publication date: September 19, 2013
    Applicant: ELITE MATERIAL CO., LTD.
    Inventors: CHEN-YU HSIEH, YI-FEI YU
  • Publication number: 20130223646
    Abstract: A speaker control method includes steps of detecting whether there is any audio signal input; outputting a first voltage signal if there is no audio signal input; outputting a second voltage signal if there is an audio signal input; and selectively turning off an audio amplifier according to the first voltage signal or turning on the audio amplifier according to the second voltage signal, wherein the audio amplifier is used for driving a speaker.
    Type: Application
    Filed: April 8, 2012
    Publication date: August 29, 2013
    Inventors: Chuan-Fu Lee, Fa-Yu Hsieh, Wei-Lun Liu
  • Publication number: 20130216140
    Abstract: An image processing system includes a difference detecting module for determining whether second image data is identical to first image data to generate a determination result, and an image processing module for processing the first image data to generate a first image processed result and selectively processing the second image data. The image processing module includes a data path and a control path. According to a reference clock signal, the first and second image data are transmitted via the data path, and the determination result is transmitted via the control path. When the determination result is affirmative, the reference clock signal provided to the data path is gated, so that, without processing the second image data, the image processing module outputs the first image processed result as a second image output corresponding to the second image data.
    Type: Application
    Filed: June 15, 2012
    Publication date: August 22, 2013
    Applicant: MStar Semiconductor, Inc.
    Inventor: Cheng-Yu Hsieh
  • Publication number: 20130197256
    Abstract: A method for the preparation of graphene is provided, which includes: (a) oxidizing a graphite material to form graphite oxide; (b) dispersing graphite oxide into water to form an aqueous suspension of graphite oxide; (c) adding a dispersing agent to the aqueous suspension of graphite oxide; and (d) adding an acidic reducing agent to the aqueous suspension of graphite oxide, wherein graphite oxide is reduced to graphene by the acidic reducing agent, and graphene is further bonded with the dispersing agent to form a graphene dispersion containing a surface-modified graphene. The present invention provides a method for the preparation of graphene using an acidic reducing agent. The obtained graphene can be homogeneously dispersed in water, an acidic solution, a basic solution, or an organic solution.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Inventors: Yi-Shuen WU, Cheng-Yu Hsieh, Cheng-Shu Peng, Jing-Ru Chen, Jun-Meng Lin, Geng-Wei Lin
  • Patent number: 8498101
    Abstract: A support frame is adapted to provide support to a display device, and includes a pivot seat module, a first support module and a second support module. The pivot seat module is adapted to be mounted to the display device for rotation relative to the display device about a first axis passing through the display device. The first support module is coupled to the pivot seat module, and is disposed to form an angle with a backside of the display device for supporting the display device at a substantially upright position. The second support module is coupled to the pivot seat module, is pivotable relative to the pivot seat module about a second axis that is orthogonal to the first axis, and cooperates with the first support module to support the display device at a lying position.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: July 30, 2013
    Assignee: Wistron Corporation
    Inventors: I-Ting Chiang, Sung-Yu Hsieh, Kuo-Hsing Wang, Chun-Chieh Chen, An-Ting Wang, Hsiu-Wei Yeh, Wei-Fan Tsai
  • Patent number: 8487675
    Abstract: A phase-locked loop (PLL) including an active filter, a voltage-controlled oscillator (VCO), two phase detectors, a charge pump and a digital-to-analog converter (DAC) is provided. The VCO generates an oscillation signal according to a control signal provided at an output of the active filter. The first phase detector generates a phase difference signal according to a reference signal and a feedback signal associating with the oscillation signal. The charge pump provides a charging current to a first input of the active filter according to the phase difference. The second phase detector generates a digital reference signal according to the phase difference between the reference signal and the feedback signal. The DAC converts the digital reference signal to an analog reference voltage and provides the analog reference voltage to the second input of the active filter.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 16, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ming-Yu Hsieh, Shih-Chieh Yen
  • Patent number: 8480003
    Abstract: A separated-flow temperature control faucet mainly comprises a constant temperature control device to mix hot water and cold water, a flow divider valve to control water flow direction and a main housing coupling with the constant temperature control device and the flow divider valve. The constant temperature control device contains an axial movement member movable axially by turning to control hot and cold water flow amount to control water temperature. The flow divider valve provides water separating function and stop function to stop water from flowing out. The faucet thus formed has a longer life span, is less likely to accumulate water dreg, can supply a greater water discharge amount, stabilize water temperature, and offer a simpler structure and improve usability.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 9, 2013
    Assignee: Deluxe Brassware Co., Ltd.
    Inventor: Yu-Yu Hsieh
  • Publication number: 20130169351
    Abstract: A transistor operating method is applicable to a transistor including a first gate, a first gate insulating layer, a semiconductor layer, a source, a drain, a second gate insulating layer and a second gate. The transistor operating method includes: grounding the first gate and the source, applying a negative bias to the second gate and applying a positive bias to the drain, so that the transistor acts as an optical detector; alternatively, grounding the source, grounding or floating the second gate, applying a bias to the first gate and applying a positive bias to the drain, so that the transistor acts as a pixel switch.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 4, 2013
    Inventors: Ting-Chang CHANG, Te-Chih Chen, Fu-Yen Jian, Tien-Yu Hsieh
  • Patent number: 8471483
    Abstract: A multi-channel LED driving system includes a power adapter, a rectifying and filtering unit, a plurality of LED strings, and a plurality of linear regulators, a CC/CV controller, an optically coupled isolator and a PWM controller. The CC/CV controller detects the conducting currents flowing though the LED strings and DC voltage source outputting from the rectifying and filtering unit, and provides voltage compensation of the power adaptor. In addition, the linear regulators slightly modulate the current difference between the LED strings to achieve current-sharing control, thus stabilize the illuminating brightness generating by the LED.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: June 25, 2013
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Chung-Shu Lee, Jung-Chang Lu, Fa-Ping Wang, Kun-Yu Hsieh
  • Patent number: 8464961
    Abstract: An electronic apparatus includes a housing and an airflow regulating device. The housing defines an accommodating space therein, and an air inlet that places the accommodating space in fluid communication with the external environment. The airflow regulating device includes a cover panel for covering and uncovering the air inlet, and an actuating mechanism coupled to the cover panel and driving movement of the cover panel to adjust the degree of opening of the air inlet in response to a change in temperature in the accommodating space so as to enhance the heat-dissipating efficiency of a cooling fan, minimize crashing and other problems due to poor heat dissipation, avoid the use of a heat-dissipating module that is high in cost and complicated in structure, and reduce manufacturing costs.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: June 18, 2013
    Assignee: Wistron Corporation
    Inventors: Wen-Chin Wu, Chi-Sung Chang, Ming-Chih Chen, Sung-Yu Hsieh
  • Patent number: 8431425
    Abstract: A method for fabricating an image sensor is provided. A substrate is provided, and then a plurality of photoresist patterns is formed on the substrate. The photoresist patterns are arranged in a first array and defined by a plurality of photomask patterns arranged as a photomask pattern array, wherein a top view of each photoresist pattern has a substantially square shape and a distance between two neighboring photoresist patterns decreases from a center of the first array toward an edge of the first array. Besides, each photomask pattern includes a transparent portion and an opaque portion, wherein an area proportion of the transparent portion included in a photomask pattern increases from the center toward the edge of the photomask pattern array. Then, a thermal reflow step is performed to convert the photoresist patterns into a plurality of microlenses arranged in a second array.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Publication number: 20130100731
    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.
    Type: Application
    Filed: March 13, 2012
    Publication date: April 25, 2013
    Inventors: Ching-Te CHUANG, Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Patent number: 8429487
    Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: April 23, 2013
    Assignee: Mediatek Inc.
    Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
  • Patent number: 8421507
    Abstract: A phase-locked loop (PLL) includes a charge pump, a frequency divider, a voltage detector, a control module, and a calibration module. When a predetermined current amount and a predetermined frequency dividing amount are provided, the voltage detector measures a voltage associated with an output frequency of the PLL to generate a first reference voltage. When a test current amount and the predetermined frequency dividing amount are provided, the voltage detector again measures the voltage to generate a second reference voltage. When the predetermined current amount and a test frequency dividing amount are provided, the voltage detector again measures the voltage to generate a third reference voltage. The control module estimates a loop gain of the PLL according to the current amounts, the frequency dividing amounts and the reference voltages. The calibration module calibrates the PLL according to the loop gain.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 16, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ming-Yu Hsieh, Shih-Chieh Yen
  • Patent number: 8395453
    Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: March 12, 2013
    Assignee: Mediatek Inc.
    Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
  • Patent number: 8390995
    Abstract: An adjusting device includes a rotating mechanism disposed between a base and a supporter for adjusting an angle between the supporter and the base, a slide mechanism disposed on the base, and a turntable mechanism slidably disposed on the slide mechanism for holding a panel module, so that the panel module can slide relative to the base along the slide mechanism and for coaxially rotating the panel module relative to the base. A contacting component of the turntable mechanism is for pushing a constraining component of the slide mechanism to pivot relative to an axle, so as to separate the constraining component from a protruding portion of the rotating mechanism for releasing constraint on the supporter relative to the base.
    Type: Grant
    Filed: July 17, 2011
    Date of Patent: March 5, 2013
    Assignee: Wistron Corporation
    Inventors: Kuo-Hsing Wang, Sung-Yu Hsieh, Yu-Min Lin
  • Publication number: 20130001667
    Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
  • Publication number: 20120305887
    Abstract: A white LED having a photoluminescent layer is provided, which includes a sapphire substrate, a gallium nitride buffer layer, an n-type gallium nitride layer, an aluminium gallium nitride multiquantum well, a p-type gallium nitride layer, a transparent conductive layer, a terbium-doped indium oxide layer as photoluminescent layer, a negative electrode, and a positive electrode, wherein the gallium nitride buffer layer, the n-type gallium nitride layer, the aluminium gallium nitride multiquantum well, the p-type gallium nitride layer, the transparent conductive layer, the terbium-doped indium oxide layer are sequentially formed on the sapphire substrate, and the negative electrode is formed on the exposed portion of the n-type gallium nitride layer and is electrically connected to the negative terminal V? of the power source, and the positive electrode is formed on the terbium-doped indium oxide layer and is electrically connected to the positive terminal V+ of the power source.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Inventors: Qing-Hua Wang, Lung-Chien Chen, Tsung-Yu Hsieh, Ching-Ho Tien
  • Patent number: 8327227
    Abstract: A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data is stored into the memory block in a block table according to the number of error correction bits in the memory block so that the sequence in which the memory block is used for storing data is determined.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 4, 2012
    Assignee: Transcend Information, Inc.
    Inventors: Chia-Ming Hu, Chun-Yu Hsieh
  • Publication number: 20120297158
    Abstract: A mass storage device capable of accessing a network storage in response to an access request of an electronic device electrically connected to the mass storage device, the mass storage device includes a first memory unit comprising a file management table for storing a first mapping relationship between a logical address and a network address of the network storage, and a controller for receiving an access request corresponding to the logical address from the electronic device and accessing a file in the network storage according to the network address through a network interface.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Inventors: Chih-Yao Hua, Chun-Yu Hsieh, Wen-Jeng Fang