Abstract: An imaging probe is suitable to be inserted into a tubular object so as to detect an interior image of the tubular object. The imaging probe includes a light source excitation assembly, an ultrasonic transducer and a receiver. The light source excitation assembly includes a pulsed laser, a first optical fiber and a cone-shaped reflecting member. The pulsed laser is suitable to generate a pulsed light energy. The cone-shaped reflecting member is suitable to reflect the pulsed light energy to let the pulsed light energy annularly irradiate the inner wall of the tubular object so as to produce a photoacoustic signal. The ultrasonic transducer is suitable to generate an ultrasonic signal. The ultrasonic signal annularly irradiates the inner wall of the tubular object so as to produce an ultrasonic echo signal. The receiver receives the photoacoustic signal and the ultrasonic echo signal.

Abstract: A support frame is adapted to provide support to a display device, and includes a pivot seat module, a first support module and a second support module. The pivot seat module is adapted to be mounted to the display device for rotation relative to the display device about a first axis passing through the display device. The first support module is coupled to the pivot seat module, and is disposed to form an angle with a backside of the display device for supporting the display device at a substantially upright position. The second support module is coupled to the pivot seat module, is pivotable relative to the pivot seat module about a second axis that is orthogonal to the first axis, and cooperates with the first support module to support the display device at a lying position.

Abstract: A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract: A low power consumption network device includes: a data rate meter for detecting a data rate of the network device; a state machine unit for determining a state of the network device according to the data rate and for generating an instruction signal; and a power control unit for controlling a power consumption state of the network device according to the instruction signal. According to the data rate, the state machine unit controls whether the network device transmits a pause frame to a link partner, so that the link partner stops transmitting data to the network device during a pause period. During the pause period, the power control unit controls the network device into a power saving mode.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.

Abstract: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.

Abstract: A faucet diverter device includes a faucet main body and a diverter valve. The faucet main body includes a first channel and a second channel for respectively passing therethrough a first fluid and a second fluid. The diverter valve, which is connected with the first channel and the second channel, includes a turning valve thereinside, a first diverting outlet, a second diverting outlet, and a pivot connected with the turning valve for turning the turning valve. The first fluid and the second fluid respectively flow into the turning valve of the diverter valve for blending with each other to generate a mixed fluid. The turning valve further includes a hole, and through turning the pivot to move the turning valve, the hole can be moved to a first position corresponding to the first diverting outlet, a second position corresponding to the second diverting outlet or a cut-off position.

Abstract: A memory management method includes fetching data corresponding to a plurality of image blocks, including at least two image blocks with different block sizes; and utilizing a memory device having a plurality of memory banks for storing the data corresponding to the plurality of image blocks. The memory management method and a related memory apparatus can make the memory device buffer motion blocks of variable sizes in an efficient way.

Abstract: An AC stress test circuit for HCI degradation evaluation in semiconductor devices includes a ring oscillator circuit, first and second pads, and first and second isolating switches. The ring oscillator circuit has a plurality of stages connected in series to form a loop. Each of the stages comprises a first node and a second node. The first and second isolating switches respectively connect the first and second pads to the first and second nodes of a designated stage and both are switched-off during ring oscillator stressing of the designated stage. The present invention also provides a method of evaluating AC stress induced HCI degradation, and a test structure.

Abstract: A separated-flow temperature control faucet mainly comprises a constant temperature control device to mix hot water and cold water, a flow divider valve to control water flow direction and a main housing coupling with the constant temperature control device and the flow divider valve. The constant temperature control device contains an axial movement member movable axially by turning to control hot and cold water flow amount to control water temperature. The flow divider valve provides water separating function and stop function to stop water from flowing out. The faucet thus formed has a longer life span, is less likely to accumulate water dreg, can supply a greater water discharge amount, stabilize water temperature, and offer a simpler structure and improve usability.

Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.

Abstract: An apparatus for determining signal power comprise an oscillating circuit and a determining circuit. The oscillating circuit generates an oscillating signal. When a to-be-detected signal has signal power greater than a threshold, the oscillating signal has a first frequency; when the signal power is smaller than the threshold, the oscillating signal has a second frequency. The determining circuit determines whether the oscillating signal has either the first frequency or the second frequency, and generates a determination result accordingly.

Abstract: A docking station for connecting a notebook computer includes a supporting frame, a connector for electrically connecting to the notebook computer, and a handle pivoted to the supporting frame. A first slot is formed on the handle, and the handle includes a pushing part for pushing the connector in a first direction. The docking station includes a first stopper, and one end of the first stopper is disposed inside the first slot of the handle. The first stopper does not stop the connector when the handle is located in a first position. The pushing part pushes the connector in the first direction so that the connector is connected to the notebook computer, and the first slot drives the first stopper in a second direction so that the first stopper stops a side of the connector when the handle rotates from a first position to a second position.

Abstract: A network device including an address move detection unit, a loop detection packet generation unit, a packet parser unit and a loop determination unit coupled to the packet parser unit is provided. The address move detection unit detects whether an address field of a first packet received by the network device is moved. The loop detection packet generation unit generates a loop detection packet if the address move detection unit detects that the address field is moved. The packet parser unit parses a second packet received by the network device to extract an information. Based on the information, the loop determination unit determines whether the second packet matches the loop detection packet so as to determine whether there is any loop existing in the network device.

Abstract: A buck-store and boost-restore converter is to be electrically connected to a pre-stage circuit, which provides a pre-stage output direct current (DC) voltage to a first capacitive load. The converter has an inductance element and is to be electrically connected to a second capacitive load. When the pre-stage output DC voltage is reduced from a first DC voltage to a second DC voltage, the inductance element outputs a current to the second capacitive load so as to transfer electric energy, which is stored in the first capacitive load, to the second capacitive load. When the pre-stage output DC voltage is raised from the second DC voltage to the first DC voltage, the inductance element outputs a current to the first capacitive load so as to transfer electric energy, which is stored in the second capacitive load, to the first capacitive load.

Abstract: An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

Abstract: An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.