Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

Abstract: The present invention provides device for generating magnetic field of calibration and built-in self-calibration (BISC) magnetic sensor and calibration method, in which a novelty structure utilized for generating a uniform, predetermined magnitude, and three-dimensional orthogonal or approximately orthogonal magnetic field of calibration is arranged in the magnetic sensor such that the magnetic sensor can perform BISC function for obtaining a calibrating information with respect to the magnetic field of calibration anytime and anywhere. The magnetic sensor can be arranged in the application device for measuring magnetic field under the real environment where the magnetic sensor is located and the calibrating information are utilized for calibrating the measuring result thereby improving and advancing the accuracy of measuring three-dimensional magnetic field.

Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first floating gate. The first floating gate transistor is connected with the first select transistor and a first program bit line. The second select transistor is connected with the source line and a first read word line. The second floating gate transistor has a second floating gate. The second floating gate transistor is connected with the second select transistor and a first read bit line. The first floating gate and the second floating gate are connected with each other.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

Abstract: The present invention provides a platform technology for testing, screening, selecting and evaluating antibiotics by using genetically engineered strains with identified, individual or combined, resistance mechanisms, prepared from fully susceptible clinical isolates. This antibiotic testing and screening system of the present invention can efficiently and effectively evaluate antibiotics against specified resistance mechanisms in vitro and in vivo, and is suitable on the novel antibiotic development in against multidrug-resistant bacteria.

Abstract: The present invention discloses a respiratory mask to connect a user and a breathing tube for receiving a first gas and releasing a second gas, so as to provide an user's respiratory system to exchange gas. It comprises a main part, an air chamber exchange part, an insert and a clamping part. The main part provides a first, second, and third openings that are communicated each other. The first opening connects to the breathing tube to receive the first gas from the breathing tube. The air chamber exchange part provides an exhaust assembly to relieve pressure according to an internal air pressure of the air chamber exchange part. The insert connects to the user's nose so as to direct the first gas to the user or direct the second gas from the user to the air chamber exchange part. The clamping part connects to the user's mouth.

Abstract: Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a portion of the approximate behaviors determined for the electronic design.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: A shift register and a gate driver circuit are provided. The shift register includes an input unit, an output unit, an electrostatic discharge unit and a reset unit. The input unit provides an input signal. The output unit is coupled to the input unit and a gate output terminal. The output unit outputs an output signal through the gate output terminal according to the input signal. The electrostatic discharge unit is coupled to the output unit. After the gate output terminal outputs the output signal, the electrostatic discharge unit pulls down a voltage of the gate output terminal according to a low gate voltage. The reset unit is coupled to the input unit and the output unit. After the electrostatic discharge unit pulls down the voltage of the gate output terminal, the reset unit resets a voltage of a bootstrap node.

Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first floating gate. The first floating gate transistor is connected with the first select transistor and a first program bit line. The second select transistor is connected with the source line and a first read word line. The second floating gate transistor has a second floating gate. The second floating gate transistor is connected with the second select transistor and a first read bit line. The first floating gate and the second floating gate are connected with each other.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Abstract: A pixel array includes first signal lines, second signal lines, active components, pixel electrodes, and selection lines. The second signal lines are intersected with and electrically insulated to the first signal lines. Each active component is electrically connected to one of the first signal lines and one of the second signal lines. Each pixel electrode is electrically connected to one of the active components. The selection lines are intersected with the first signal lines to form a plurality of first intersections and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections but electrically insulated to the first signal lines at second intersections. The selection lines are electrically insulated to the second signal lines. At least one of the second signal lines is disposed between each selection line and any one of the active components.

Abstract: A conductive structure includes a first wire, a second wire, and a conductive pillar. The second wire is disposed over the first wire and intersected with the first wire. The conductive pillar is disposed between the first wire and the second wire. A bottom surface area of the conductive pillar is greater than an area at which the first wire overlaps the conductive pillar.

Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.