Abstract: An IC structure includes a substrate, a deep n-well (DNW), a first device, a second device, a first electrical path and a second electrical path. The DNW is in the substrate. The first device is formed inside the DNW and connected to a first lower reference voltage and a first higher reference voltage. The second device is formed in the substrate and outside the DNW, and connected to a second lower reference voltage and a second higher reference voltage. The first electrical path is electrically connected between the first device and the second device. The second electrical path is electrically connected between the first lower reference voltage and the second lower reference voltage. A second metal layer that includes the second electrical path is located in an area outside of an area above a first metal layer in which the first electrical path is located.

Abstract: A post of a tool wagon is provided, including a hollow structure thereinside, further including at least one slide, each of the at least one slide extending along a lengthwise direction of the post, each of the at least one slide being configured for a partition to be slidably installed thereto, wherein at least one said slide is configured with at least one engagement mechanism disposed therewithin, each of the at least one engagement mechanism includes a through opening arranged on the post and a blocking portion, the blocking portion extends in the hollow structure. A tool wagon is also provided, including a plurality of the posts described above.

Abstract: The present disclosure relates generally to depot formulations of lurasidone and methods of making depot formulations of lurasidone. The depot formulations include a suspending agent and are highly syringeable.

Abstract: Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of solutions may be generated with the second discretization scheme and the plurality of inputs.

Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.

Abstract: A cable clip disposed at an electronic device and adapted to clamp a cable is provided. The cable clip comprises a first clamping unit and a second clamping unit. The first clamping unit has a first clamping portion and two spaced-apart anti-pulling portions. The second clamping unit has a second clamping portion corresponding in position to the first clamping portion and two fixing portions corresponding in position to the two anti-pulling portions, to which the two anti-pulling portions are connected respectively. The cable is clamped between the first and second clamping portions when the first and second clamping units fit together in operation, and thus part of the electronic device is confined between the two anti-pulling portions, allowing the first clamping unit to bear a pulling force by one of the two anti-pulling portions. The cable clip prevents detachment of the cable's connector otherwise electrically connected to the electronic device.

Abstract: A display apparatus including a display panel and a driver circuit is provided. The display panel includes a display region and a non-display region. The non-display region includes a plurality of dummy pixels connected to one another. The driver circuit provides gate driving voltages and a test data voltage, so as to make the dummy pixels connected to one another generate a charging rate test signal in response to the test data voltage.

Abstract: A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.

Abstract: A turbine inspection stopper is provided, including a main body and a pressure gauge. The main body has a base portion, an annular flange which is laterally disposed around the base portion and an air passage, the annular flange is for being connected to one of two ends of a turbine, the base portion and the annular flange define an interior space, the interior space is for communicating with an interior of the turbine, and the air passage is for communicating with outside and the interior of the turbine; and at least one part of the pressure gauge is buried in the main body and communicates with the interior space.

Abstract: An improved passivation structure for GaN field effect transistor comprising at least one dielectric layer formed on a top surface of a GaN field effect transistor and a passivation layer formed on a top surface of the dielectric layer. The GaN field effect transistor has a gate electrode comprising a Schottky contact metal layer, at least one diffusion barrier metal layer and a high conductivity metal layer. The passivation layer is made of a low cure temperature Polybenzoxazole (PBO) which can be cured at a low-temperature. Thereby the intermixing of the Schottky contact metal layer and the the diffusion barrier metal layer are prevented.

Abstract: A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.

Abstract: A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.

Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.

Abstract: The present disclosure relates to a modular solar power generation apparatus comprising a base plate, a light guiding unit, a plurality of connection units and a plurality of solar panels wherein: the light guiding unit is installed on the base plate; all connection units are circlewise mounted on the base plate and encircling the light guiding unit; each the solar panel, which is connected to one of the connection units, and the base plate form an angle of inclination by which each the solar panel features upward broadened widths such that any two neighboring solar panels allow their corresponding edges to be adjacent to each other and a gap in between to be narrowed for development of solar panels easily installed and maintained.

Abstract: The various implementations described herein include methods, devices, and systems for automatic audio equalization. In one aspect, a method is performed at an audio device having one or more processors, memory, and a plurality of device interface elements, including one or more speakers and a plurality of microphones. The method includes: (1) detecting a change in orientation of the audio device from a first orientation to a second orientation; and (2) in response to detecting the change in orientation, configuring operation of two or more of the plurality of device interface elements.

Abstract: An optical communication mount configured for surface mounting of optical transmitters, receivers or transceivers. The mount includes a housing having holes extending from the back side to the front side of the housing. The mount includes a first set of electrically-conductive traces disposed on a bottom side of the housing for surface mounting the mount on a printed circuit board (PCB), and a second set of electrically-conductive traces disposed on the front side of the housing. The mount also includes optical fibers extending into the thru-holes from the back side of the housing. The mount includes photo devices substantially registered with the thru-holes at the front side of the housing in a manner to receive and/or transmit more optical signals by way of the optical fibers, wherein the photo devices are configured to receive bias voltages from the PCB by way of the first and second sets of electrically-conductive traces.

Abstract: A smoke generator is provided, including a smoke generating unit and an airflow system. The airflow system has an air inlet passage, an air outlet passage and a vacuum generator, the vacuum generator communicates with the air inlet passage and the air outlet passage, and the vacuum generator has a suction portion communicating with the smoke generating unit.