Patents by Inventor An Zhang

An Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230238067
    Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 27, 2023
    Inventors: XiangNan Zhao, Yali Song, An Zhang, Hongtao Liu, Lei Jin
  • Patent number: 11690924
    Abstract: A modular system of locker banks for receipt and delivery of packages is described. The system may include associate modules each having one or more lockers and a control board in communication with each of the lockers in the module. Each locker may include a locker board having a processor and memory configured to control operation of the locker. Each locker may include a lock and a light. The system may further include one or more control modules, each having the above components and further including a kiosk having one or more input and output devices for entering information to the module for controlling operation of the system. The modular system may be connected to a server and/or an administrator terminal.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: July 4, 2023
    Assignee: Digilock Asia Ltd.
    Inventors: Asil Gokcebay, Ali Ozhan, An Zhang
  • Publication number: 20230207027
    Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
  • Patent number: 11676665
    Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 13, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kaiwei Li, Jianquan Jia, Hongtao Liu, An Zhang
  • Patent number: 11676646
    Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: June 13, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shan Li, Kaikai You, Ying Cui, Jianquan Jia, Kaiwei Li, An Zhang
  • Patent number: 11665905
    Abstract: A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qiguang Wang, Lei Jin, An Zhang, Jianwei Lu
  • Patent number: 11655653
    Abstract: An electronic lock cylinder that may be a direct replacement for a European-style standard cylinder is disclosed. The lock cylinder may include a core, a first shaft rotatably mounted in the core, and a second shaft rotatably mounted in the core and coaxial with the first shaft. A first cam and a second cam may be each rotatably mounted in the core and coaxial with the first shaft. The first cam may include a first lug and the second cam may include a second lug, where the first lug and the second lug may each be coupled to a deadbolt. A clutch may be disposed on the first shaft and shiftable from a first position to a second position, and a motor may be disposed in the core and operatively coupled to the clutch and configured to shift the clutch from the first position to the second position.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: May 23, 2023
    Assignee: Digilock Asia Ltd.
    Inventors: An Zhang, Asil Gokcebay
  • Patent number: 11626170
    Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 11, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
  • Patent number: 11615667
    Abstract: A modular system of locker banks for receipt and delivery of packages is described. The system may include associate modules each having one or more lockers and a control board in communication with each of the lockers in the module. Each locker may include a locker board having a processor and memory configured to control operation of the locker. Each locker may include a lock and a light. The system may further include one or more control modules, each having the above components and further including a kiosk having one or more input and output devices for entering information to the module for controlling operation of the system. The modular system may be connected to a server and/or an administrator terminal.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 28, 2023
    Assignee: Digilock Asia Ltd.
    Inventors: Asil Gokcebay, Ali Ozhan, An Zhang
  • Publication number: 20220282552
    Abstract: Embodiments of the present invention disclose a logic intelligent control system of train door based on intelligent control unit. The system comprises: a first intelligent control unit located in a selected vehicle of a train, a second intelligent control unit located in each of the other remaining vehicles of the train, and a door controller located in each vehicle. The first intelligent control unit is configured to output corresponding door control instructions through the corresponding door control instruction output port after acquiring door control operation information; the door control instruction input ports corresponding to the first intelligent control unit and the second intelligent control units are configured to drive corresponding door controller control ports to control the door controllers of a corresponding vehicle to execute the door control instruction after receiving the door control instructions.
    Type: Application
    Filed: April 22, 2020
    Publication date: September 8, 2022
    Inventors: An ZHANG, Jianying LIANG, Bowen JIANG, Chuanming SUN, Mengyang SHI
  • Publication number: 20220084573
    Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 17, 2022
    Inventors: Shan Li, Kaikai You, Ying Cui, Jianquan Jia, Kaiwei Li, An Zhang
  • Patent number: 11241740
    Abstract: The invention relates to a method for preparing high-melting-point metal powder through multi-stage deep reduction, and belongs to the technical field of preparation of powder. The method includes the following steps of mixing dried high-melting-point metal oxide powder with magnesium powder and performing a self-propagating reaction, placing an intermediate product into a closed reaction kettle, leaching the intermediate product with hydrochloric acid as a leaching solution so as to obtain a low-valence oxide MexO precursor of the low-valence high-melting-point metal; uniformly mixing the precursor with calcium powder, pressing the mixture, placing the pressed mixture into a vacuum reduction furnace, heating the vacuum reduction furnace to 700-1200° C., performing deep reduction for 1-6 h, leaching a deep reduction product with hydrochloric acid as a leaching solution and performing treatment, so as to obtain the high-melting-point metal powder.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 8, 2022
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Ting An Zhang, Zhihe Dou, Yan Liu, Zimu Zhang, Guozhi Lv, Qiuyue Zhao, Liping Niu, Daxue Fu, Weiguang Zhang
  • Patent number: 11225411
    Abstract: A method for producing insoluble sulfur, including: heating a sulfur to 200-700° C., quenching it with water, aqueous solution and other solvents, drying and solidifying the resulting substance at 40-80° C. for 3-15 h, to obtain an insoluble sulfur crude product; crushing the crude product in water into particles with a particle size of 50-400 meshes, wherein the water temperature is not higher than 80° C.; pumping the slurry of water and crude product into the upper part of an extraction column, pumping solvent into the lower part thereof; making the water and solvent from the top of the column flow into a separation tank to separate water phase and solvent phase, heating and evaporating the solvent phase to recover solvent and obtain soluble sulfur; heating and evaporating the insoluble sulfur and solvent from the bottom of the column to recover solvent and obtain purified insoluble sulfur.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 18, 2022
    Assignee: China University of Petroleum (East China)
    Inventors: Yanzhen Wang, Chunmin Song, Hongling Duan, An Zhang, Li Gao
  • Publication number: 20220013177
    Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Kaiwei Li, Jianquan Jia, Hongtao Liu, An Zhang
  • Patent number: 11222674
    Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 11, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shan Li, Kaikai You, Ying Cui, Jianquan Jia, Kaiwei Li, An Zhang
  • Patent number: 11205494
    Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: December 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jianquan Jia, Kaikai You, Ying Cui, Kaiwei Li, Yali Song, Shan Li, An Zhang
  • Publication number: 20210358948
    Abstract: A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Qiguang Wang, Lei Jin, An Zhang, Jianwei Lu
  • Patent number: D934658
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 2, 2021
    Assignee: Digilock Asia Ltd.
    Inventors: An Zhang, Asil Gokcebay
  • Patent number: D941611
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: January 25, 2022
    Inventor: An Zhang
  • Patent number: D992998
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: July 25, 2023
    Assignee: Digilock Asia Ltd.
    Inventors: An Zhang, Asil Gokcebay