Abstract: Methods for selective inhibition control in semiconductor manufacturing are provided. An example method includes providing a substrate including a feature having one or more feature openings and a feature interior. A nucleation layer is formed on a surface of the feature interior. Based on a differential inhibition profile, a nonconformal bulk layer is selectively formed on a surface of the nucleation layer to leave a region of the nucleation layer covered, and a region of the nucleation layer uncovered by the nonconformal bulk layer. An inhibition layer is selectively formed on the covered and uncovered regions of the nucleation layer. Tungsten is deposited in the feature in accordance with the differential inhibition profile.

Abstract: Methods of mitigating line bending during feature fill include deposition of an amorphous layer and/or an inhibition treatment during fill.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Provided herein are methods of filling features with metal including inhibition of metal nucleation. One aspect of the disclosure relates to a method including providing a substrate having a feature and field regions, wherein the feature is to be filled with metal, the feature including feature surfaces and a feature opening; performing an inhibition treatment to inhibit metal deposition on at least some of the feature surfaces; after performing the inhibition treatment, performing a first chemical vapor deposition (CVD) operation including exposing the feature to a metal precursor and hydrogen (H2); after performing the first CVD operation, performing a de-inhibition treatment to decrease inhibition; and after decreasing inhibition, performing a second CVD operation to deposit metal in the feature and/or on the field regions.

Abstract: Methods of filling a features of partially fabricated semiconductor substrates with metal include depositing a gradient metal nitride layer in the feature. The gradient metal nitride layer decreases in thickness and/or nitrogen concentration with feature depth. At the top of the feature, the gradient metal nitride layer can serve as an adhesion layer during a subsequent planarization. Because the gradient metal nitride layer deceases in thickness and/or nitrogen concentration further into the feature, it occupies less volume in the mid-section and bottom section of the feature. This improves resistivity in the feature. The feature is filled with metal.

Abstract: Improved edge rings with flow conductance features are disclosed. The flow conductance features of the edge ring are features added to the edge ring that adjust the flow conductance of gas flowing in the local area of the edge ring. The flow conductance features can adjust the flow conductance to compensate for features on a semiconductor wafer, the edge ring, and in the chamber that may affect the flow of gas in the local areas. The flow conductance may be increased, reduced, or tuned depending on the desired effect.

Abstract: Methods of mitigating line bending during feature fill include deposition of an amorphous layer and/or an inhibition treatment during fill.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Provided herein are systems and methods for semiconductor processing including feature fill processes. The methods comprise providing a substrate having a feature to be filled with a metal in a chamber, and flowing a metal precursor and a reducing agent into the chamber to deposit metal in the feature in a chemical vapor deposition (CVD) operation, wherein the CVD operation comprises a ramp down stage in which the flow rate of the metal precursor into the chamber is ramped down from a first flow rate to a second flow rate. or a ramp up stage in which the flow rate of the metal precursor into the chamber is ramped up from the first flow rate to the second flow rate.

Abstract: Provided herein are methods of depositing low stress and void free metal films in deep features and related apparatus. Embodiments of the methods include treating the sidewalls of the holes to inhibit metal deposition while leaving the feature bottom untreated. In subsequent deposition operations, metal precursor molecules diffuse to the feature bottom for deposition. The process is repeated with subsequent inhibition operations treating the remaining exposed sidewalls. By repeating inhibition and deposition operations, high quality void free fill can be achieved. This allows high temperature, low stress deposition to be performed.

Abstract: Methods of depositing a tungsten nucleation layers that achieve very good step coverage are provided. The methods involve a sequence of alternating pulses of a tungsten-containing precursor and a boron-containing reducing agent, while co-flowing hydrogen (H2) with the boron-containing reducing agent. The H2 flow is stopped prior to the tungsten-containing precursor flow. By co-flowing H2 with the boron-containing reducing agent but not with the tungsten-containing precursor flow, a parasitic CVD component is reduced, resulting in a more self-limiting process. This in turn improves step coverage and conformality of the nucleation layer. Related apparatuses are also provided.

Abstract: Methods of mitigating line bending during feature fill include deposition of a nucleation layer having increased roughness. In some embodiments, the methods include depositing two or more metal nucleation layers.

Abstract: Provided herein are methods of depositing low stress and void free metal films in deep features and related apparatus. Embodiments of the methods include treating the sidewalls of the holes to inhibit metal deposition while leaving the feature bottom untreated. In subsequent deposition operations, metal precursor molecules diffuse to the feature bottom for deposition. The process is repeated with subsequent inhibition operations treating the remaining exposed sidewalls. By repeating inhibition and deposition operations, high quality void free fill can be achieved. This allows high temperature, low stress deposition to be performed.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

Abstract: Methods and apparatuses for forming low resistivity tungsten using tungsten nitride barrier layers are provided herein. Methods involve depositing extremely thin tungsten nitride barrier layers prior to depositing tungsten nucleation and bulk tungsten layers. Methods are applicable for fabricating tungsten word lines in 3D NAND fabrication as well as for fabricating tungsten-containing components of DRAM and logic fabrication. Apparatus included processing stations with multiple charge volumes to pressurize gases in close vicinity to a showerhead of a processing chamber for processing semiconductor substrates.

Abstract: Providing herein are methods of delivery of gas reactants to a processing chamber and related apparatus.

Abstract: Provided herein are methods of filling features with metal including inhibition of metal nucleation. Also provided are methods of enhancing inhibition and methods of reducing or eliminating inhibition of metal nucleation.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include providing a backside inhibition gas as part of a deposition-inhibition-deposition (DID) sequence.