Patents by Inventor Anand Chandrashekar
Anand Chandrashekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210305059Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.Type: ApplicationFiled: June 15, 2021Publication date: September 30, 2021Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
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Publication number: 20210257194Abstract: An exhaust system for a substrate processing system includes a radical generator configured to receive a gas mixture including halogen species and to generate halogen radicals, a first pump to pump exhaust gas from an exhaust outlet of a processing chamber, and a first valve configured to selectively fluidly connect an outlet of the radical generator to the first pump downstream from the outlet of the processing chamber.Type: ApplicationFiled: June 14, 2019Publication date: August 19, 2021Inventors: Krishna BIRRU, Gang LIU, Leonard KHO, Anand CHANDRASHEKAR, Gishun HSU
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Patent number: 11075115Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: GrantFiled: September 6, 2018Date of Patent: July 27, 2021Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 11069535Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.Type: GrantFiled: May 26, 2020Date of Patent: July 20, 2021Assignee: Lam Research CorporationInventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
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Patent number: 10977405Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.Type: GrantFiled: January 29, 2019Date of Patent: April 13, 2021Assignee: Lam Research CorporationInventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
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Patent number: 10916434Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: February 10, 2020Date of Patent: February 9, 2021Assignee: Lam Research CorporationInventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Publication number: 20200347497Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Damodar Shanbhag, Guangbi Yuan, Thadeous Bamford, Curtis Warren Bailey, Tony Kaushal, Krishna Birru, William Schlosser, Bo Gong, Huatan Qiu, Fengyuan Lai, Leonard Wai Fung Kho, Anand Chandrashekar, Andrew H. Breninger, Chen-Hua Hsu, Geoffrey Hohn, Gang Liu, Rohit Khare
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Publication number: 20200286743Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
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Patent number: 10760158Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.Type: GrantFiled: April 16, 2018Date of Patent: September 1, 2020Assignee: Lam Research CorporationInventors: Damodar Shanbhag, Guangbi Yuan, Thadeous Bamford, Curtis Warren Bailey, Tony Kaushal, Krishna Birru, William Schlosser, Bo Gong, Fengyuan Lai, Leonard Wai Fung Kho, Anand Chandrashekar, Andrew H. Breninger, Chen-Hua Hsu, Geoffrey Hohn, Gang Liu, Rohit Khare, Huatan Qiu
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Publication number: 20200242209Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
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Publication number: 20200185225Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: February 10, 2020Publication date: June 11, 2020Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Publication number: 20200185273Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 10580695Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: May 29, 2018Date of Patent: March 3, 2020Assignee: Lam Research CorporationInventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 10580654Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: GrantFiled: November 13, 2018Date of Patent: March 3, 2020Assignee: Lam Research CorporationInventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Patent number: 10566211Abstract: Methods for etching tungsten and other metal or metal-containing films using a nitrogen-containing etchant gas are provided. The methods involve exposing the film to a continuous wave (CW) plasma and switching to a pulsed plasma toward the end of the etching operation. The pulsed plasma has a lower concentration of nitrogen radicals and can mitigate the effects of nitridation on the tungsten surface. In some embodiments, subsequent deposition on etched surfaces is performed with no nucleation delay. Apparatuses for performing the methods are also provided.Type: GrantFiled: August 28, 2017Date of Patent: February 18, 2020Assignee: Lam Research CorporationInventors: Anand Chandrashekar, Madhu Santosh Kumar Mutyala
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Publication number: 20190326168Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin, Deqi Wang, Gang Liu, Michal Danek, Siew Neo
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Patent number: 10395944Abstract: Methods and apparatuses for filling features with metal materials such as tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a metal such as a tungsten-containing material followed by removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ratio feature. The portion may be removed by exposing the tungsten-containing material to a plasma generated from a fluorine-containing nitrogen-containing gas and pulsing and/or ramping the plasma during the exposure.Type: GrantFiled: May 1, 2018Date of Patent: August 27, 2019Assignee: Lam Research CorporationInventors: Waikit Fung, Liang Meng, Anand Chandrashekar
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Patent number: 10381266Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.Type: GrantFiled: July 3, 2017Date of Patent: August 13, 2019Assignee: Novellus Systems, Inc.Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin
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Publication number: 20190206731Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: March 6, 2019Publication date: July 4, 2019Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20190185999Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.Type: ApplicationFiled: April 16, 2018Publication date: June 20, 2019Inventors: Damodar Shanbhag, Guangbi Yuan, Thadeous Bamford, Curtis Warren Bailey, Tony Kaushal, Krishna Birru, William Schlosser, Bo Gong, Huatan Qiu, Fengyuan Lai, Leonard Wai Fung Kho, Anand Chandrashekar, Andrew H. Breninger, Chen-Hua Hsu, Geoffrey Hohn, Gang Liu, Rohit Khare