Patents by Inventor Anand Chandrashekar
Anand Chandrashekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9589835Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.Type: GrantFiled: July 2, 2013Date of Patent: March 7, 2017Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun
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Publication number: 20170053811Abstract: Methods and apparatuses for filling features with metal materials such as tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a metal such as a tungsten-containing material followed by removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ratio feature. The portion may be removed by exposing the tungsten-containing material to a plasma generated from a fluorine-containing nitrogen-containing gas and pulsing and/or ramping the plasma during the exposure.Type: ApplicationFiled: August 18, 2016Publication date: February 23, 2017Inventors: Waikit Fung, Liang Meng, Anand Chandrashekar
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Publication number: 20170040214Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.Type: ApplicationFiled: August 19, 2015Publication date: February 9, 2017Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-tien Su, Wenbing Yang, Michael Wood, Michal Danek
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Patent number: 9548228Abstract: Methods of depositing tungsten in different sized features on a substrate are provided herein. The methods involve depositing a first bulk layer of tungsten in the features, etching the deposited tungsten, depositing a second bulk tungsten, which is interrupted to treat the tungsten after the smaller features are completely filled, and resuming deposition of the second bulk layer after treatment to deposit smaller, smoother tungsten grains into the large features. The methods also involve depositing tungsten in multiple cycles of dep-etch-dep, where each cycle targets a group of similarly sized features using etch chemistry specific for that group, and depositing in groups from smallest sized features to the largest sized features. Deposition using methods described herein produce smaller, smoother grains with void-free fill for a wide range of sized features in a substrate.Type: GrantFiled: July 25, 2014Date of Patent: January 17, 2017Assignee: Lam Research CorporationInventors: Anand Chandrashekar, Raashina Humayun
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Publication number: 20160343612Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: May 16, 2016Publication date: November 24, 2016Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
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Publication number: 20160190008Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: ApplicationFiled: December 10, 2015Publication date: June 30, 2016Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20160118345Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
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Publication number: 20160093528Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: September 25, 2015Publication date: March 31, 2016Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20160071764Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.Type: ApplicationFiled: February 22, 2013Publication date: March 10, 2016Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 9240347Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: GrantFiled: September 30, 2014Date of Patent: January 19, 2016Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Patent number: 9236297Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.Type: GrantFiled: December 4, 2013Date of Patent: January 12, 2016Assignee: Novellus Systems, Inc.Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
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Patent number: 9082826Abstract: Disclosed herein are methods of filling a 3-D structure of a semiconductor substrate with a tungsten-containing material. The 3-D structure may include sidewalls, a plurality of openings in the sidewalls leading to a plurality of features having a plurality of interior regions. The methods may include depositing a first layer of the tungsten-containing material within the 3-D structure such that the first layer partially fills a plurality of interior regions of the 3-D structure, etching vertically and horizontally after depositing the first layer, and depositing a second layer of the tungsten-containing material within the 3-D structure after the vertical and horizontal etching such that the second layer fills at least a portion of the interior regions left unfilled by the first layer. Also disclosed herein are apparatuses for filling a 3-D structure of a semiconductor substrate with a tungsten-containing material having a controller with instructions for etching vertically and horizontally.Type: GrantFiled: May 22, 2014Date of Patent: July 14, 2015Assignee: Lam Research CorporationInventors: Anand Chandrashekar, Joydeep Guha, Raashina Humayun, Hua Xiang
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Patent number: 9034768Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.Type: GrantFiled: July 9, 2010Date of Patent: May 19, 2015Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
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Publication number: 20150056803Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
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Publication number: 20150024592Abstract: Methods of depositing tungsten in different sized features on a substrate are provided herein. The methods involve depositing a first bulk layer of tungsten in the features, etching the deposited tungsten, depositing a second bulk tungsten, which is interrupted to treat the tungsten after the smaller features are completely filled, and resuming deposition of the second bulk layer after treatment to deposit smaller, smoother tungsten grains into the large features. The methods also involve depositing tungsten in multiple cycles of dep-etch-dep, where each cycle targets a group of similarly sized features using etch chemistry specific for that group, and depositing in groups from smallest sized features to the largest sized features. Deposition using methods described herein produce smaller, smoother grains with void-free fill for a wide range of sized features in a substrate.Type: ApplicationFiled: July 25, 2014Publication date: January 22, 2015Inventors: Anand Chandrashekar, Raashina Humayun
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Publication number: 20140349477Abstract: Disclosed herein are methods of filling a 3-D structure of a semiconductor substrate with a tungsten-containing material. The 3-D structure may include sidewalls, a plurality of openings in the sidewalls leading to a plurality of features having a plurality of interior regions. The methods may include depositing a first layer of the tungsten-containing material within the 3-D structure such that the first layer partially fills a plurality of interior regions of the 3-D structure, etching vertically and horizontally after depositing the first layer, and depositing a second layer of the tungsten-containing material within the 3-D structure after the vertical and horizontal etching such that the second layer fills at least a portion of the interior regions left unfilled by the first layer. Also disclosed herein are apparatuses for filling a 3-D structure of a semiconductor substrate with a tungsten-containing material having a controller with instructions for etching vertically and horizontally.Type: ApplicationFiled: May 22, 2014Publication date: November 27, 2014Inventors: Anand Chandrashekar, Joydeep Guha, Raashina Humayun, Hua Xiang
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Patent number: 8883637Abstract: A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.Type: GrantFiled: June 28, 2012Date of Patent: November 11, 2014Assignee: Novellus Systems, Inc.Inventors: Esther Jeng, Anand Chandrashekar, Raashina Humayun, Michal Danek, Ronald Powell
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Patent number: 8835317Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.Type: GrantFiled: May 6, 2013Date of Patent: September 16, 2014Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
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Publication number: 20140162451Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.Type: ApplicationFiled: December 4, 2013Publication date: June 12, 2014Applicant: Novellus Systems, Inc.Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
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Publication number: 20140017891Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.Type: ApplicationFiled: July 2, 2013Publication date: January 16, 2014Inventors: Anand Chandrashekar, Raashina Humayun